Graphics processor with staggered memory timing

Details Graphics processor with staggered memory timing Graphics processor with staggered memory timing

1988-09-13

1991-02-05

Harkcom, Gary V.

Boots, shoes, and leggings

364521, 340750, G06F 1340

Patent

active

049911104

ABSTRACT:
A graphics processor is coupled to a plurality of RAMs (Random Access Memories) for storing a frame of a display. The processor provides a separate RAS (Row Address Strobe) signal and a separate CAS (Column Address Strobe) signal to each of the memories so that row and/or column addresses to each of the RAMs can be latched using a staggered timing sequence. Data can be written into or read from memory using this staggering technique, wherein overall data transfer rate is faster than the memory cycle time of each of the RAMs.

REFERENCES:
patent: 4673930 (1987-06-01), Bujalski et al.
patent: 4674064 (1987-06-01), Vaughn
patent: 4796232 (1989-01-01), House
patent: 4800530 (1989-01-01), Itoh et al.
patent: 4814969 (1989-03-01), Kiyooka
patent: 4903217 (1990-02-01), Gupta et al.

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