Graphics processor enhancement unit

Details Graphics processor enhancement unit Graphics processor enhancement unit

1994-02-02

1996-09-24

Powell, Mark R.

395164, G06F 1500

Patent

active

055599508

ABSTRACT:
A graphics processor enhancement system having a processor connected through data and lower address lines to two areas of random access memory (RAM). One area of RAM stores an image frame and the other area of RAM stores a copy of a background section of the image frame. The processor is connected through a read/write line and higher address lines to a programmable logic device (PLD), the output of which functions to enable one of the two areas of RAM. The system also stores a transparent memory map containing a copy of the object surrounded by transparent pixel values. The processor provides an animated display by modifying a portion of the image frame, such that an object stored therein is incremental moved across the image frame. The PLD enables the processor to read the copied background section, overlay this background section with the transparent memory map and write the resulting combination to the image frame over the old object stored therein. The resulting image frame includes the object at a new location.

REFERENCES:
patent: 5170468 (1992-12-01), Shah
patent: 5254984 (1993-10-01), Wakeland
patent: 5388192 (1995-02-01), Ohsawa

Affiliated with

Also associated with

Rating

Graphics processor enhancement unit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Graphics processor enhancement unit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Graphics processor enhancement unit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1947220