Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
1999-07-15
2003-02-11
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
Reexamination Certificate
active
06518971
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to computer systems and, more particularly, the invention relates to processing graphics request data for display on a computer display device.
BACKGROUND OF THE INVENTION
Three dimensional graphics request data commonly is processed in a computer system as a plurality of polygons having vertices. Each of the vertices has associated attribute data (e.g., color, transparency, depth, etc . . .) that is utilized to rasterize pixels on a computer display device. Vertices commonly are processed by computer systems as a plurality of contiguous polygons, known in the art as “polygon strips.”
Many computer systems utilize a graphics accelerator for processing incoming polygon strips. Moreover, graphics accelerators commonly include a plurality of parallel processors for processing different portions (i. e., substrips) of incoming polygon strips. To that end, accelerators with parallel processors typically include a single polygon strip breaker for dividing the incoming polygon strip into a plurality of substrips. The substrips may be distributed to each of the processors in any convenient manner such as, for example, in a round-robin fashion. Each processor thus processes different substrips. Breaking a polygon strip, however, requires that certain vertices at the boundaries of substrips be processed by two processors. Accordingly, more data is transmitted from a single breaker than is received. This can slow processing by the graphics accelerator.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, a graphics accelerator having first and second processors includes a first vertex breaker unit (“first breaker”) coupled to the first processor, and a second vertex breaker unit (“second breaker”) coupled to the second processor. The first breaker divides an incoming polygon strip into a first set of substrips, while the second breaker divides the incoming polygon strip into a second set of substrips. The graphics accelerator further includes a bus coupled with the first and second breakers for transmitting the incoming polygon strip to the first breaker and the second breaker.
The first processor produces a first set of output substrips, and the second processor produces a second set of output substrips. In preferred embodiments, the graphics accelerator further has a first sequencer for sequencing the first set of output substrips into a preselected order. The first breaker may include a sequence number generator for applying a sequence number to each of the substrips in the first set of substrips. In a similar manner, the graphics accelerator also may include a second sequencer for sequencing the second set of substrips. In preferred embodiments, the first set of substrips and second set of substrips include no common substrips.
In other embodiments of the invention, the first processor includes a plurality of first subprocessors, where each of the first subprocessors has a current workload. The current workload of a given subprocessor preferably is the total number of substrips that the given subprocessor is processing at a current time. The first breaker directs each substrip in the first set of substrips to the plurality of subprocessors based upon each of the current workloads of each of the plurality of first subprocessors. In preferred embodiments, the first breaker directs substrips to the one of the first subprocessors with the smallest current workload.
In preferred embodiments, the first breaker includes a counter for determining when to divide the incoming polygon strip for processing by the first processor. The first breaker may include an input for receiving the incoming polygon strip (having a first size), and an output for transmitting output data having a second size. The first size preferably is greater than the second size.
In accordance with other aspects of the invention, a graphics accelerator for processing an incoming polygon strip includes a first processor, a second processor, a first breaker coupled with the first processor for dividing the incoming polygon into a first set of substrips, and a second breaker coupled with the second processor for dividing the incoming polygon strip into a second set of substrips. The first breaker has a first input for receiving the incoming polygon strip, and the second breaker has a second input for receiving the incoming polygon strip. In preferred embodiments, the first set of substrips is different from the second set of substrips.
In yet other aspects of the invention, a graphics accelerator for processing an incoming polygon strip includes a plurality of strip processors, and a plurality of breakers, where each of the breakers receives the incoming polygon strip. Each strip processor preferably includes a breaker for breaking the incoming polygon strip into a set of substrips and processes sets of substrips that are different than the sets of substrips processed by the other strip processors.
In preferred embodiments, each of the breakers includes a sequencer for sequencing substrips in a preselected order. The preselected order for a given strip processor is the order that the substrips are received by the given strip processor.
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Iwashita, et al., “A Fine Grained Data Flow Machine and
Pesto, Jr. William S.
Schroter Russell
Young David
3Dlabs Inc. Ltd.
Bockhop & Reich, LLP
Tung Kee M.
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