Graphics memory system that utilizes look-ahead paging for reduc

Details Graphics memory system that utilizes look-ahead paging for reduc Graphics memory system that utilizes look-ahead paging for reduc

1998-05-12

2000-06-20

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

345521, 345508, 345422, G09G 500, G06F 1316

Patent

active

060783362

ABSTRACT:
The present invention provides a graphics memory system comprising at least one memory controller that utilizes a first-in-first-out (FIFO) memory architecture in combination with a look-head paging technique for paging a frame buffer memory having a multi-bank architecture. The memory controller controls accessing of a frame buffer memory of the graphics memory system. The frame buffer memory comprises a multi-bank architecture, which preferably is a two-bank architecture. The FIFO architecture comprises a plurality of FIFO memory devices (FIFOs). The memory controller is capable of determining whether a particular FIFO contains no more transactions for a particular bank and, if not, of causing that bank to be re-paged for a different FIFO. In this respect, the memory controller performs what is referred to herein as "inter-FIFO" look-ahead paging. Each of the FIFOs preferably comprises intelligence to enable it to perform look-ahead paging within that particular FIFO, or "intra-FIFO" look-ahead paging. In this respect, each FIFO comprises intelligence that enables it to analyze the entries stored in it to determine whether one bank can be re-paged by the memory controller while the other bank is being accessed by the memory controller.

REFERENCES:
patent: 6000019 (1999-12-01), Dykstal et al.
patent: 6002412 (1999-12-01), Schinnerer

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