Graphics frame buffer with strip Z buffering and programmable Z

Details Graphics frame buffer with strip Z buffering and programmable Z Graphics frame buffer with strip Z buffering and programmable Z

1987-08-18

1990-10-02

Clark, David L.

Boots, shoes, and leggings

340798, G06F 314

Patent

active

049611534

ABSTRACT:
A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. This allows one RAM in each group to be accessed with a memory cycle in unison with one RAM in each other group, up to the number of groups. During such a memory cycle each RAM can receive a different address. A tile is the collection of pixel locations associated with a collection of addresses sent to the RAM's. Because of the regular nature of the permutations these locations may be regions bounded by a single boundary that may be rectangular and of varying size and shape. Changing the mapping of (X, Y) pixel addresses to RAM addresses for the groups changes the size and shape of the tiles. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separate cache. Caching allows the principle of locality to substitute shorter bit-cycles to the cache for memory cycles to the frame buffer, resulting in improved memory throughput. The Z buffer for hidden surface removal need not be a full size frame buffer, as a lesser portion of frame buffer is, if need be, used repeatedly. The location of such a lesser size Z buffer in the overall frame buffer is programmable.

REFERENCES:
patent: 3602702 (1971-08-01), Warnock
patent: 4660157 (1987-04-01), Beckwith et al.
patent: 4679041 (1987-07-01), Fetter et al.
patent: 4731864 (1988-03-01), Modla

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