Graphics frame buffer with programmable tile size

Details Graphics frame buffer with programmable tile size Graphics frame buffer with programmable tile size

1990-08-08

1991-10-08

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 1562

Patent

active

050560441

ABSTRACT:
A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. This allows one RAM in each group to be accessed with a memory cycle in unison with one RAM in each other group, up to the number of groups. During such a memory cycle each RAM can receive a different address. A tile is the collection of pixel locations associated with a collection of addresses sent to the RAMs. Because of the regular nature of the permutations these locations may be regions bounded by a single boundary that may be rectangular and of varying size and shape. Changing the mapping of (X, Y) pixel addresses to RAM addresses for the groups changes the size and shape of the tiles. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separate cache. Caching allows the principle of locality to substitute shorter bit-cycles to the cache for memory cycles to the frame buffer, resulting in improved memory throughput.

REFERENCES:
patent: 4742474 (1988-05-01), Knierim
patent: 4755810 (1988-07-01), Knierim
patent: 4958302 (1990-09-01), Fredrickson et al.
patent: 4961153 (1990-10-01), Fredrickson et al.

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