Graphics display subsystem that allows per pixel double buffer d

Computer graphics processing and selective visual display system – Display driving control circuitry – Physically integral with display elements

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

345203, G09G 500

Patent

active

056297238

ABSTRACT:
A graphics display subsystem that allows rejection of double buffer display of pixel data in a graphics layer is provided. The subsystem has a memory containing a plurality of pixels represented by binary bits, wherein each pixel is divided into two or more sub-pixel fields, and wherein one or more bits of a particular sub-pixel field of a given pixel are set to a predetermined double buffer reject value when the given pixel corresponds to a single buffer display application. A double buffer reject circuit compares one or more bits of a double buffer sub-pixel field of a given pixel with a predetermined double buffer reject value to determine equality of the one or more bits and the predetermined value, wherein the given pixel is represented by binary bits and wherein the given pixel is divided into two or more sub-pixel fields including the double buffer sub-pixel field. The double buffer reject circuit receives a buffer select signal selecting one of the two or more sub-pixel fields of the given pixel to be accessed during a current display frame. In response, the double buffer reject circuit accesses the selected sub-pixel field of the given pixel when the buffer select signal does not select the double buffer sub-pixel field or when the buffer select signal selects the double buffer sub-pixel field and the comparison does not show equality, and further the double buffer reject circuit accesses one of the two or more sub-pixel fields of the given pixel that is not the double buffer sub-pixel field when the buffer select signal selects the double buffer sub-pixel field and the comparison shows equality. A digital-to-analog converter in communication with the double buffer reject circuit receives the pixel data contained in the sub-pixel field accessed by the double buffer reject circuit and converts the pixel data into analog video signals for driving a monitor display device.

REFERENCES:
patent: 4668994 (1987-05-01), Takahashi et al.
patent: 4700181 (1987-10-01), Maine et al.
patent: 4823108 (1989-04-01), Pope
patent: 4864517 (1989-09-01), Maine et al.
patent: 4875034 (1989-10-01), Brokenshire
patent: 4910683 (1990-03-01), Bishop et al.
patent: 4945495 (1990-07-01), Ueda
patent: 5061919 (1991-10-01), Watkins
patent: 5065368 (1991-11-01), Gupta et al.
patent: 5101365 (1992-03-01), Westberg et al.
patent: 5264837 (1993-11-01), Buehler
patent: 5300948 (1994-04-01), Tsujido et al.
patent: 5402147 (1995-03-01), Chen et al.
patent: 5426725 (1995-06-01), Kilgore
patent: 5452235 (1995-09-01), Isani
patent: 5457482 (1995-10-01), Rhoden et al.
patent: 5543824 (1995-08-01), Priem et al.
Aranda, M. & Henderson, R.L., "Dual Frame Buffer . . . ", IBM Technical Disclosure Bulletin, vol. 36 No. 04, Apr. 1993.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Graphics display subsystem that allows per pixel double buffer d does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Graphics display subsystem that allows per pixel double buffer d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Graphics display subsystem that allows per pixel double buffer d will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1388853

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.