Graphics accelerator with dual memory controllers

Details Graphics accelerator with dual memory controllers Graphics accelerator with dual memory controllers

1994-11-03

1997-09-02

Powell, Mark R.

Computer graphics processing and selective visual display system

Computer graphic processing system

Interface

345503, 345516, 345520, 345526, 345200, G06F 1316, G06F 1516, G06F 1206

Patent

active

056641621

ABSTRACT:
A processor having two separate and relatively independent memory controllers to achieve a dual interface architecture. A first memory controller is coupled to the host interface for retrieving data and instructions and a second memory controller is coupled to an independent local bus for interfacing with a frame buffer memory. A depth buffer may also be coupled to the local bus if desired. Address multiplexor logic is preferably included to allow either memory controller to address either external bus. Multiplexor and buffer logic is also preferably included to allow data transfer in either direction. Preferably, the processor is a graphics processor and both memory controllers are programmable for different addressing formats, such as linear and X/Y in the preferred embodiment. In this manner, data is transferred from host to local memories, and vice versa, in any desired format without delays due to memory controller reconfiguration. Data transfers from one location to another within a single memory, such as window moves within the frame buffer, are achieved much faster. Dual memory controllers allow command or instruction prefetching during execution of a previous command. More sophisticated graphics functions, such as texture mapping and data alignment, are also performed much faster and more efficiently.

REFERENCES:
patent: 5522027 (1996-05-01), Matsumoto et al.
patent: 5522082 (1996-05-01), Guttag et al.
patent: 5560030 (1996-09-01), Guttag et al.

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