Graphics accelerator having minimal logic multiplexer system for

Details Graphics accelerator having minimal logic multiplexer system for Graphics accelerator having minimal logic multiplexer system for

1996-10-15

1998-08-18

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

327 99, 327408, H03K 17693

Patent

active

057962880

ABSTRACT:
A minimal logic multiplexer system using tri-state drivers with one-hot enabling lead, provides high-speed access to processor elements by any one of a plurality of control units. The multiplexer system is implemented in a manner that minimizes the circuit implementation, minimizes gate delay within the circuit implementation, and allows processing instructions to pass from a control unit to the processor elements by way of multiplexed control lines therebetween. The multiplexer system contains control unit gate groups that are enabled and disabled in parallel by a select lead. Each control unit gate group can be implemented internal to the respective control unit or external in a common intermediary multiplexer circuit location.

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patent: 5475324 (1995-12-01), Tomiyori

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