Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements
Reexamination Certificate
1999-04-29
2002-06-18
Bayerl, Raymond J. (Department: 2773)
Computer graphics processing and selective visual display system
Display driving control circuitry
Controlling the condition of display elements
C345S215000, C345S215000, C345S215000, C345S215000, C702S057000, C702S066000, C702S067000, C702S068000
Reexamination Certificate
active
06407756
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to logic analyzer user interfaces, and more particularly to a user interface that allows simplified clock selection.
BACKGROUND OF THE INVENTION
As known by those skilled in the art, a logic analyzer is an electronic instrument used to detect, analyze, and display digital voltage signals. Logic analyzers provide many configuration functions as a result of the increasing operational complexity of target devices. In many measurement applications, however, not all of the configuration functions are needed to obtain simple measurements—that is, the necessary configuration functions are selected in accordance with level of measurement complexity.
Conventional logic analyzers include a graphical user interface that allows a user to make selections with respect to the configuration functions. The graphical user interface is generally made available on a display integrated with the logic analyzer, and may additionally be made available on a remote terminal that communicates with the logic analyzer. In prior art logic analyzers, the user is required to make selections with respect to all the configuration functions, even if the desired measurements do not require some of the configuration functions. The user must select a “don't care” value with respect to an unnecessary configuration function. These unnecessary configuration function setting operations are time-consuming. Furthermore, the complex array of a configuration settings renders the setup of the logic analyzer confusing to unskilled or unfamiliar users of the logic analyzer.
A logic analyzer generally allows data sampling in one of two clock modes—either state mode or timing mode. In a state mode measurement, the logic analyzer is clocked by a signal from the system under test. Each time the clock signal becomes valid, the analyzer samples data from the system under test. Since the analyzer is clocked by the system, state measurements are synchronous with the test system. In a timing measurement, the logic analyzer samples data at regular intervals according to a clock signal internal to the timing analyzer. Since the analyzer is clocked by a signal that is not related to the system under test, timing measurements capture traces of electrical activity over time. These measurements are asynchronous with the test system.
Clock setup must be correctly accomplished in order for a synchronous sampling (i.e., state mode) measurement to be acquired by the logic analyzer. In previous user interface implementations, the portion of the user interface which facilitates the specification of clocks has been distributed over several unrelated setup windows accessed from within the logic analyzer's graphical user interface. A prior art graphical user interface clock setup dialog is shown in
FIGS. 1 and 2
.
FIG.
1
(
a
) is a prior art logic analyzer user interface illustrating an example setup window
2
of a prior art logic analyzer. Setup window
2
comprises four tabs: Config tab
20
which allows the user to set up the measurement configuration of a machine, Format tab
40
which allows the user to setup the format in which to display the captured measurements, Trigger tab
60
which allows the user to set up the point on which data is captured, and Symbol tab
80
which allows the user to map alphanumeric symbols to raw data.
FIG.
1
(
a
) displays the Config tab
20
. The Config tab
20
selections are displayed by clicking, using a mouse, on the Config tab
20
. The Config tab
20
selections tell the logic analyzer how the hardware (i.e., the available logic analyzer pods) is connected. In the illustrative embodiment, the logic analyzer allows the user to define and connect to up to two different machines, in the illustrative embodiment named MACHINE
1
and MACHINE
2
. In this embodiment, the logic analyzer is capable of operating as a two-analyzer machine and represents both machines under the Config tab
20
, allowing the user to rename the machines to any names desired. The assigned names are shown wherever appropriate under the other tabs to identify the associated machine settings.
Config tab
20
comprises a machine window
21
and
31
for each machine. Each machine window
21
and
31
comprises a respective name display
22
and
32
to identify its associated machine, and a respective machine type button
24
and
34
which toggles either to a timing type or a state type, or an “off” state in which the machine does not operate. The setting of the machine type button
24
and
34
communicates to the logic analyzer to operate either as a timing analyzer or a state analyzer. In FIG.
1
(
a
), MACHINE
1
is set to operate in timing mode, and MACHINE
2
is set to off.
Each machine window
21
and
31
also comprises an assigned pod window
26
and
36
, which displays the pods assigned to that particular machine. In the illustrative embodiment, pods A
1
and A
2
are assigned to MACHINE
1
, and MACHINE
2
has no pods assigned to it. Each pod A
1
, A
2
, A
3
, A
4
, A
5
and A
6
has a clock associated with it, labeled J, K, L, M, N and P, respectively. The user assigns pods to one or the other of the two machines by selecting a pod displayed in the unassigned pod window
38
and dragging it to the assigned pod window
26
or
36
as appropriate. Activity occurring on each pin of a pod is displayed as a double arrow. No activity is displayed as a dash.
Once the machine type and assigned pods are set up, the user must obtain the format selections by clicking the Format tab
40
, shown in FIG.
1
(
b
). The format selections tell the logic analyzer how to use its internal resources Format tab
40
includes an operating mode button
51
, which defines the operating mode of the machine. In the example of FIG.
1
(
b
), MACHINE
1
is set to operate in timing mode at 333 MHz, with a memory depth of 128K samples. Format tab
40
includes a data level button
43
,
53
for each assigned pod indicated by labels
42
,
52
, which defines the data levels of the signals received on each channel associated with the respective pod. In addition, Format tab
40
includes a set of labels
44
for bits or sets of bits that will be monitored during a measurement (also called a “trace”). The user may define the labels
44
associated with bits or sets of bits of the assigned pods. Each label has a clock definition control
45
, a first associated pod definition control
46
, and a second associated pod definition control
47
. The user clicks on the desired pod definition control
45
,
46
,
47
, which activates a pop-up menu
59
that allows the user to click on the individual bits of the ass pod definition to define which bits to monitor. The monitored bits are displayed with a “*”, and the un-monitored bits are displayed with a “.”. An activity indicator line
48
indicates which bits are active by displaying a “
”.
Once the format of the data and clock lines are set up, the user clicks on the Trigger tab
60
, shown in FIG.
1
(
c
), to set up the trigger. A trigger is a reference event around which information is gathered. For example, in a logic analyzer, the user might wish to trigger on a glitch on a hardware line when operating in timing mode, or on an entry to a subroutine in software when operating in state mode. Logic analyzers use the trigger specification to determine when to start storing data. When beginning, the trigger might be set up on the first occurrence of any kind (trigger on “anystate”). As the user learns more about the problem, the trigger specification might be modified to enter more specific trigger conditions. A trigger specification is a set of conditions that must be true before the instrument triggers.
Trigger tab
60
includes an “Arming Control” button
61
that allows the user to set up the arming sequence between the two machines MACHINE
1
and MACHINE
2
. A logic analyzer machine must be armed before it can search for its trigger condition. Typically, machines are armed immediately when a “Run” or a “Group Run” is selected. A
Roeca Jeffrey Erickson
Simon Frank D
Sontag David N
Agilent Technologie,s Inc.
Bayerl Raymond J.
Nguyen Thomas T.
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