Graphic system for masking multiple non-contiguous bytes having

Details Graphic system for masking multiple non-contiguous bytes having Graphic system for masking multiple non-contiguous bytes having

1996-04-10

1999-08-03

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

Distributed processing system

712224, 711122, 711159, G06F 1310, G06F 1208

Patent

active

059319453

ABSTRACT:
A partial store instruction and associated logic for storing selected bytes of a group of bytes in a register to a designated memory location. A mask in a separate register is used to enable particular bytes to be written, with only enabled bytes being written to the final location. The mask can be previously generated as a result of a comparison or other operation. The creation of the mask and the execution of a partial store instruction can also be used as a prefetch instruction, eliminating the need for a separate opcode for a prefetch.

REFERENCES:
patent: 3820078 (1974-06-01), Curley
patent: 5193167 (1993-03-01), Sites et al.
patent: 5357267 (1994-10-01), Inoue
patent: 5506980 (1996-04-01), Inagami et al.
460-469, 1990.
T. I. (TMS32010 User's Guide) pp. 3-7, 1983.

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