Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
1998-06-24
2001-01-09
Tung, Kee M. (Department: 2776)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S213000, C345S520000, C345S520000, C345S501000
Reexamination Certificate
active
06172686
ABSTRACT:
BACKGROUNDS OF THE INVENTION
1. Field of the Invention
The present invention relates to a graphic processor and a graphic processing method to process figures to be displayed on a display unit by use of a microcomputer, and particularly relates to a graphic processor and a graphic processing method suitable for a system to rapidly display a plurality of figures in motion with three-dimensionally overlaying them.
2. Description of the Related Art
Recently, various special functions are required for pictures displayed on a graphic display unit so as to improve the effect appealing to the viewers' perception. One of such special functions is the stereoscopic display. It is an expression technique to display a three-dimensional scene with a depth having a plurality of mutually overlaid figures (sprites) in rapid motion and change on the screen of a graphic display unit.
Referring to
FIGS. 4
,
5
and
6
, a conventional graphic processor and a graphic processing method used for stereographic display are described below.
FIG. 4
shows a stereoscopic display screen displaying a first figure G
1
comprising 4*4 pixels at the coordinates (
40
, m) and a second different figure G
2
comprising 4*4 pixels at the coordinates (
42
, n) on the first line of a display screen SC
1
with the second figure G
2
displayed in front of the first figure G
1
.
FIG. 5
is a block diagram illustrating the configuration of a graphic processor and the signal flow and
FIG. 6
is a timing chart of the signal waveforms when the figures in
FIG. 4
are displayed.
As shown in
FIG. 5
, a conventional graphic processor
20
comprises a drawing processor
21
, a timing generator
22
and a display buffer
23
and outputs the graphic display data to a display
24
as a graphic display unit. The timing generator
22
has input of the clock signal (S
1
), the vertical sync signal (S
3
) and the horizontal sync signal (S
2
) and outputs the drawing processor control signal (S
4
), the display initialize signal (S
8
) and the drawing display switching signal (S
11
). The drawing processor
21
incorporates a storage to store the original data of the displayed figure. It receives the input of the clock signal (S
1
), the drawing processor control signal (S
4
) and the display initialize signal (S
8
) for certain drawing processing and outputs graphic data comprising the drawing graphic data signal (S
5
), the display buffer write enable signal (S
6
) and the display buffer drawing address signal (S
7
). The display buffer
23
temporarily stores the graphic data and outputs the graphic display data to the display
24
in response to input of the drawing display switching signal (S
11
).
Next, referring to
FIG. 6
, the operation of the graphic processor
20
when displaying the first line as shown in
FIG. 4
is described below.
Firstly, at the same time as the activation of the graphic processor
20
, the vertical sync signal (S
2
) is input from the main system (not shown) to the graphic processor
20
and the timing generator
22
is initialized. Note that rewriting of the whole contents in the display buffer to the graphic data to display the same color as the screen background color (i.e. no display on the screen) is referred to as the display initialization in the description below. The graphic data to display the same color as the screen background color is called the transparent data. In other words, the transparent data is the graphic data of the same color as that of the screen background so that it causes nothing to be displayed on the screen. The background color is usually specified by the user.
Next, prior to the operation to display figures on the screen updated periodically, the graphic processor
20
is initialized for every update of the screen. For this, once for every update of the screen, the horizontal sync signal (S
3
) is input from the main system (not shown) to the timing generator
22
. Upon input of the horizontal sync signal (S
3
), the drawing processor control signal (S
4
), the display initialize signal (S
8
) and the drawing display switching signal (S
11
) are output from the timing generator
22
.
The drawing processor
21
is initialized by the display initialize signal (S
8
) and then the display buffer
23
is initialized by the display initialize signal from the drawing processor
21
. These processes bring the graphic processor
20
to the drawing start status.
Referring to
FIG. 6
, initialization of the graphic processor
20
starts when the drawing display switching signal (S
11
) reaches the low level (hereinafter indicated as “0” (L)) and is executed while the display initialize signal (S
8
) is at “0” (L). Corresponding to the display buffer drawing address signal (S
7
)=“0” to “n” (number of display buffers), transparent data is provided as the drawing graphic data signal (S
5
). Meanwhile, in response to the display buffer drawing address signal (S
7
), the display buffer write enable signal (S
6
) becomes “0” (L). Thus, by replacing the data at the addresses used for display in the display buffer
23
entirely with transparent data, initialization of the display buffer
23
is completed.
Upon completion of initialization of the display buffer
23
, the display initialize signal (S
8
) rises to the high level (hereinafter indicated as “1” (H)) and terminates the initialization process of the graphic processor
20
. Then, the graphic processor
20
is in the drawing start status, where graphic data can be stored to the display buffer
23
.
The drawing processor
21
firstly displays the figure G
1
with a low display priority as shown in FIG.
4
. For this, it serially outputs, as the graphic data, the display buffer drawing address signal (S
7
)=“40” to “43” (h) and the corresponding drawing graphic data signal (S
5
) for every clock signal (S
1
). During this period, corresponding to the display buffer drawing address signal (S
7
), the display buffer write enable signal (S
6
) becomes “0” (L) and the drawing graphic data signal (S
5
), the display buffer write enable signal (S
6
) and the display buffer drawing address signal (S
7
) are stored to the display buffer
23
as the graphic data of the figure G
1
.
Then, the drawing processor
21
displays the figure G
2
as shown in FIG.
4
. For this, it serially outputs, as the graphic data, the display buffer drawing address signal (S
7
)=“42” to “45” (h) and the corresponding drawing graphic data signal (S
5
) for every clock signal (S
1
). During this period, corresponding to the display buffer drawing address signal (S
7
), the display buffer write enable signal (S
6
) becomes “0” (L) and the drawing graphic data signal (S
5
), the display buffer write enable signal (S
6
) and the display buffer drawing address signal (S
7
) are stored to the display buffer
23
as the graphic data of the figure G
2
.
Upon completion of operation to store the graphic data for drawing to the display buffer
23
, the drawing display switching signal (S
11
) becomes “1” (H) and the graphic processor
20
moves to the graphic display status. Then, the graphic processor
20
reads out the graphic data from the display buffer
23
and starts its output as the graphic display data signal. After moving to the graphic display status, the drawing processor
21
provides the display buffer
23
with the display buffer drawing address signal (S
7
)=“0” to “n”. Thus, the corresponding display data signal (S
9
) is taken out from the display buffer
23
and output to the display
24
. By these processes above, the figures G
1
and G
2
are displayed on the display screen as shown in FIG.
4
.
Then, referring to
FIGS. 4
,
7
,
8
and
9
, another example of the conventional graphic processor is described below.
FIG. 7
is a block diagram to illustrate the configuration of a graphic processor and the signal flow,
FIG. 8
is a block diagram to show the configuration of a status register and
FIG. 9
is a timing chart of the signal waveforms when the figures in
FIG. 4
are displayed.
As shown in
FIG. 7
, a
NEC Corporation
Scully Scott Murphy & Presser
Tung Kee M.
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