Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
1998-12-17
2002-05-07
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S545000, C345S531000, C345S639000, C345S620000, C345S660000
Reexamination Certificate
active
06384831
ABSTRACT:
BACKGROUND OF THE INVENTION
In general, the present invention relates to a technology for preventing flickering, which might be generated in an operation based on interlaced scanning in display of image information which is to be displayed using a non-interlace scanning technique. More particularly, the present invention relates to an effective technology applied to a graphic processor for displaying computer data and for controlling rendering operations, as well as to a data processing system employing such a graphic processor.
A graphic processor employed in a computer apparatus, such as a personal computer, supplies image data generated by an application program to a display device, such as a video signal synchronized to the display timing of the display device. The computer apparatus controls the display of the image data by adopting a non-interlace scanning system. In the non-interlace scanning system, interlaced scanning of scanning fields is not carried out. Instead, all scanning lines are scanned in each vertical scanning period. Thus, a screen can be created in one vertical scanning period. As a result, a high display quality with little flickering can be obtained.
In an interlaced scanning system such as used in a conventional television, receiver on the other hand, scanning lines are divided into even and odd fields. In each vertical scanning period, only one of the even and odd fields are scanned. That is, interlaced scanning of every other scanning line is carried out. As a result, one complete screen is created in two vertical scanning periods.
As described above, in the non-interlace scanning system, all scanning lines are scanned in each vertical scanning period. Thus, the vertical-direction position of a scanned scanning line is the same for all screens. In the interlaced scanning system, however, a screen comprising only even fields and a screen comprising only odd fields are displayed in alternate vertical scanning periods. Thus, the vertical-direction position of a scanned scanning line appearing on the current screen is shifted from the immediately preceding and succeeding screens by one scanning-line pitch, respectively. As a result, if the difference in image information, such as the difference in brightness and color, between adjacent scanning lines in the interlaced scanning system is big, flickering is generated easily between a screen comprising only even fields and a screen comprising only odd fields.
In addition, there is also a need to display high-resolution image data produced by a personal computer on an ordinary television set by converting the data into a video signal of typically the NTSC (National Television System Committee) system. If such computer image data is displayed on a television set by merely changing the scanning system, however, a flickering will be generated which is not seen in the case of displaying the same data on a display device using the non-interlace scanning system. This is because, in comparison with a natural image produced by a television broadcasting system, a video camera or a VTR/VCR (video tape recorder/video cassette recorder), for example computer image data mainly comprises lines of characters and shade patterns, exhibiting a big difference in image information between any two adjacent upper and lower scanning lines. For example, assume that pixels of three adjacent upper, middle and lower scanning lines at positions on the same vertical column are black, white and black, providing big differences in brightness among the adjacent pixels. In this case, since two adjacent black and white pixels are displayed on two different screens, flickering is seen.
Technologies for eliminating such flickering have been disclosed in Japanese Patent Laid-open Nos. Hei 6-83299, Hei 7-274086, Hei 6-46299 and Hei 8-317311. While there are differences in detail among these technologies, in the case of either of the technologies, a display control system is provided with a plurality of line buffers each used for storing image information of a scanning line. More particularly, the same plurality of line buffers are used for storing image information of the current scanning line and pieces of information of preceding scanning lines. Image information of the current scanning line is corrected by using the pieces of information of preceding scanning lines in order to prevent differences in image information among the scanning lines from becoming big.
SUMMARY OF THE INVENTION
In order to be capable of operating synchronously with a display timing, a line buffer must be implemented by an SRAM (Static Random-Access Memory) having a high speed. According to what has been disclosed in the documents cited above, a plurality of line buffers are required. Thus, a graphic control circuit composed of a large number of line buffers inevitably increases the cost of the display control circuit. In addition, according to the technologies adopted by the display control system for eliminating flickering, correction is carried out in an operation to output image data, after processing of the image data has been completed and the data has been stored in a frame buffer, synchronously with display scanning. In the prior technologies, processing to eliminate flickering by consideration of a source image prior to the rendering process is not carried out. In addition, with the prior technologies, freedom to arbitrarily determine the degree of processing is not taken into consideration.
It is thus an object of the present invention to provide a graphic processor and a data processing system which are capable of reducing a difference in image information between any two adjacent scanning lines without the need to newly add a line buffer.
It is another object of the present invention to provide a graphic processor and a data processing system which are capable of preventing flickering which might be generated in the display of image information produced originally for a non-interlace scanning display device by adopting the interlaced scanning technique, without the need to newly add a line buffer.
It is still another object of the present invention to provide a graphic processor and a data processing system which are capable of freely carrying out a processing to eliminate flickering of the screen caused by differences in resolution among pieces of image information in the display of the pieces of image information by overlaying one piece over another using the interlace scanning technique, without the need to newly add a line buffer.
It is a further object of the present invention to provide a low-cost graphic processor having an instruction for eliminating flickering.
It is a further object of the present invention to provide a data processing system capable of carrying out image-data processing to eliminate flickering by using a frame buffer memory.
The above and other objects, as various well as novel characteristics of the present invention will become more apparent from a study of the description provided in this specification with reference to the accompanying drawings.
Representative overviews of the present invention as disclosed in this application will be explained briefly as follows.
As shown in
FIG. 1
, a graphic processor
1
according to a first aspect of the present invention includes a rendering control circuit
2
for controlling an operation to draw image data on a memory unit
4
used as a frame buffer in accordance with a result of interpretation of a command, and a display control circuit
3
for controlling an operation to read out image data from the memory unit
4
in a scanning direction synchronously with a display scanning timing. Pieces of image data of source image information are laid out in the memory unit
4
to form a pixel-data matrix corresponding to a matrix of pixels with rows of the pixel-data matrix oriented in parallel to the scanning direction and columns thereof oriented perpendicularly to the scanning direction. The rendering control circuit
2
is capable of carrying out blend processing for correcting the sourc
Nakamura Atsushi
Nakatsuka Yasuhiro
Yamagishi Kazushige
Antonelli Terry Stout & Kraus LLP
Chauhan Ulka J.
Hitachi , Ltd.
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