Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reissue Patent
1992-12-03
2001-03-20
Zimmerman, Mark K. (Department: 2772)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S519000, C345S520000, C345S520000
Reissue Patent
active
RE037103
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a graphic processing apparatus for processing graphic data stored in a memory, and in particular, to a graphic processing apparatus in which the number of memories to be employed can be reduced so as to minimize the size of the processing apparatus.
For example, the Japanese Patent Publication JP-A-60-136793 descibes a graphic processing apparatus in which characters and graphic data are generated in a display memory (frame buffer) so as to be delivered to output devices such as a display and a printer. In this conventional, example a high-speed graphic drawing operation is achieved by use of a method in which data bits constituting at least one pixel are packed in a word so as to be stored in the memory. In contrast with the prior method in which information of a pixel requires a plurality of words, this method allows accessing of the memory in the unit of a word (16 bits); in consequence, by packing information of a pixel in a single word, at least one pixel can be updated through one access, which therefore increases the processing speed.
In the conventional example above, although the memory is connected to a 16-bit data bus, the dynamic random access memory (DRAM) generally possesses a 1-bit or 4-bit data bus, and hence at least four to 16 memory elements are required, which prevents the apparatus from being miniturized.
In addition, the Japanese Patent Publication JP-A-60- 225888 describes an apparatus including a dynamic random access memory (DRAM) having a nibble function (one of consecutive data read functions); however, description has not been given of a combination with a graphic processor in which data are accessed in a parallel fashion.
Moreover, in the Japenese Patent Publication JP-A-55-129387, there is described a system for transferring serial data between a processor and an external device; however, parallel data access is carried out between the processor and a memory.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a small-sized graphic processing apparatus in which data transfer is enabled through a data bus having a reduced bit width so as to minimize the number of memory elements employed.
In order to achieve the object above, according to the present invention, there is disposed data converting means between processor means processing parallel data and a memory so as to enable the data bus width of the memory to be smaller than that of the processor means. The data converting means includes a latch for temporarily storing read data and a multiplexer for writing data The present invention is characterized in that a memory having a successive data read function is applied to a processor effecting parallel data processing.
In the graphic processing apparatus according to the present invention, the memory is accessed in a time shared fashion such that data is converted by the converting means into parallel data. That is, in a data reading operation, data sequentially read out in a time shared fashion is temporarily stored in a latch so as to be supplied as parallel data to the processor. Moreover, in a data writing operation, parallel data supplied from the processor is sequentially written through the multiplexer into the memory in a time shared fashion.
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Katsura Koyo
Kojima Shin-ichi
Kurakami Noriyuki
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Zimmerman Mark K.
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