Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
1999-06-08
2001-04-24
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S520000
Reexamination Certificate
active
06222563
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a graphic processing apparatus for generating, displaying or printing characters and graphic data, and more particularly to a graphic processing apparatus including a frame buffer provided integrally in a main memory to store display pixel data and a graphic processing method of generating characters and graphic data.
A graphic processing apparatus for generating and displaying characters and graphic data includes a frame buffer for storing data corresponding to pixels on a display screen. In order to display a stable picture on the display screen, it is necessary to read data from the frame buffer successively repeatedly in synchronism with the raster scanning of a display unit. In order to realize the display function, the frame buffer is generally used as a memory independently of a main memory.
Japanese Patent Unexamined Publication JP-A-59-131979 discloses, as a special purpose memory suitable for the frame buffer, a graphic dual-port memory having a serial output port in addition to a random access port. The use of the memory can make short the display access and hence improve the drawing performance (graphic generation). However, thereafter, even if the integration density of the memory is increased, a constant number of memories are required to obtain a fixed display output. Accordingly, there is a problem that the high integration is not utilized in a lower capacity area of the memory effectively.
Further, there are Japanese Patent Unexamined Publications JP-A-63-91787 and JP-A-1-265348 as relevant references.
Heretofore, there is a problem that the access method which is complicated and low in a speed must be utilized in order to cope with various applications. Further, there is a problem that the high integration of the graphic dual-port memory capable of being used as the high-speed frame buffer is not utilized for a small capacity memory.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a graphic processing apparatus and method in which a frame buffer and a main memory are configured integrally and a high-speed and standard dynamic memory with simple configuration is used to effectively utilize the integration degree of the memory.
Further, it is another object of the present invention to provide a graphic processing apparatus in which a standard dynamic RAM can be used to make high-speed drawing with a high-integrated and small configuration.
In the present invention, successive column access for a memory is used in which a row address is designated and then data in different column addresses within the designated row address are successively accessed, and there is provided means for buffering a series of data between the access by a processor and the access to the memory. Display graphic information is also stored in a main memory in addition to a program and data.
Further, in order to achieve the high-speed drawing, there is provided a graphic processor which performs the successive column access for a dynamic memory. The number of times of the column accesses is varied and there is provided buffer means for temporarily storing data obtained by the column accesses.
The buffer means can absorb deviation in a timing between the access from the processor and the memory access having a higher throughput than that of the access from the processor and utilize empty memory access as display access.
Further, the graphic processor allows to vary the number of times of the column accesses and performs the graphic processing for raster data having any length effectively.
According to the present invention, since the frame buffer and the main memory can be configured integrally, it can be configured simply and small regardless of the high-speed operation. For example, 32 to 64 16-Mbit memory elements are used to operate a processor having a performance of 100 MIPS or more effectively and 1280×1024 pixels can display 16 million colors (8 bits for each of R, G and B).
Further, according to the present invention, system bus access (access by operation processing means) and display access (access by display control means) can be controlled preferentially in accordance with its priority order and waste of the memory access can be eliminated.
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Nikkei Electronics, No. 653, pp. 16-17, Jan. 15, 1996.
Fujita Ryo
Fukunaga Yasushi
Katsura Koyo
Koga Kazuyoshi
Nishida Takehiko
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Tung Kee M.
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