Optics: measuring and testing – Standard
Reexamination Certificate
2000-12-04
2002-10-01
Font, Frank G. (Department: 2877)
Optics: measuring and testing
Standard
C250S252100
Reexamination Certificate
active
06459482
ABSTRACT:
TECHNICAL FIELD
The present invention relates to nanometerology and in particular to calibration methods, calibration standards, and systems critical dimension scanning electron microscopy.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these higher device densities there have been, and continue to be, efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish higher device densities, smaller and smaller features sizes are required. These may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and surface geometry of corners and edges of various features.
High resolution lithographic processes are used to achieve small features. In general, lithography refers to processes for pattern transfer between various media. In lithography for integrated circuit fabrication, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist. The film is selectively exposed with radiation (such as optical light, x-rays, or an electron beam) through an intervening master template, the mask, forming a particular pattern. Exposed areas of the coating become either more or less soluble than the unexposed areas (depending on the type of coating) in a particular solvent developer. The more soluble areas are removed with the developer in a developing step. The less soluble areas remain on the silicon wafer forming a patterned coating. The pattern corresponds to the image of the mask or its negative. The patterned resist is used in further processing of the silicon wafer.
At various stages in forming the patterned resist coating and processing the silicon wafer, it is desirable to measure critical dimensions resulting from the lithographic process. Critical dimensions include the size of features in the wafer or patterned resist such as line widths, line spacing, and contact dimensions. Due to the extremely fine patterns involved, scanning electron microscopy (SEM) is often employed to analyze critical dimensions. Specialized critical dimension measuring SEM systems have been developed for use with silicon wafers, which are of a size that makes them too large for most SEM systems.
In SEM, an electron beam is scanned across the sample. The beam interacts with the sample to produce measurable responses that vary with position over the course of a scan. Measurable responses include backscattering of electrons and production of secondary electrons, auger electrons, X-rays and cathodoluminescence. Secondary electrons are the most useful of the measurable responses in accessing surface topography and are the responses most often employed in critical dimension analysis.
Although SEM systems measure critical dimensions with high precision, they must be calibrated frequently for the measurements to be accurate. Precision refers to the capability of distinguishing small differences in dimension. Accuracy refers to the correctness of measurements in absolute terms. Precise measurements are reproducible, but contain systematic errors that must be quantified and taken into account for the measurements to be accurate. Calibration quantifies systematic errors and is carried out on a regular basis in SEM systems, usually at least once a day.
Calibration involves taking measurements on a calibration standard. A calibration standard is a sample having accurately known dimensions. One calibration standard commonly employed is a periodic pattern formed into a silicon substrate. Such a calibration sample is simple, but has low contrast and easily becomes contaminated over the course of extended use.
Another type of calibration standard is formed with a patterned polysilicon coating over a silicon wafer. A thin layer of silicon oxide is used to facilitate binding between the patterned polysilicon and the wafer. A similar calibration standard is formed with a uniform polysilicon coating over the silicon oxide layer and has a calibration patterned formed in another silicon oxide coating that is formed over the polysilicon. These calibration standards can be used with very low electron beam energies, howvere, due to the insulating properties of the silicon oxide, at higher beam energies these calibration standards undesirably accumulate charges that affect the electron beam and skew calibration measurements.
Another calibration standard, described in Yang et al., U.S. Pat. No. 6,048,743, includes a semiconductor wafer, an insulating first patterned layer formed on the wafer, a plurality of contacts electrically communicating with the wafer and formed between the pattern of the first insulating layer, a conductive layer formed over the first insulating layer and in electrical communication with the wafer through the contacts, and a second insulating layer with a second pattern formed over the conductive layer. The conductive layer electrically communicates between the second insulating layer and the wafer and permits charges to drain from the second insulating layer to the wafer during scanning. An example is provided in which the second insulating layer is polysilicon. The accuracy of this calibration standard is limited by the roughness of the edges of features formed by the patterned polysilicon layer and is not commensurate with the resolving power of some electron microscopes.
Despite the availability of SEM system calibration standards, there remains an unsatisfied need for SEM system calibration standards and calibration methods with improved accuracy.
SUMMARY OF THE INVENTION
The present invention provides SEM systems, SEM calibration standards, and SEM calibration methods that improve accuracy in critical dimension measurements. The calibration standards have features formed with an amorphous material including amorphous silicon. These feature have smooth side walls and provide a calibration standard with desirable such as sharp edges, high contrast, well characterized spacial dimensions, low cost, and high durability.
One aspect of the invention provides a calibration standard for an SEM system including a silicon wafer and a patterned coating containing amorphous silicon, wherein the patterned coating is over the silicon wafer and the patterned coating is in electrical communication with the silicon wafer.
Another aspect of the invention provides a calibration standard for an SEM system including a silicon wafer, a conductive layer over the silicon wafer, and a patterned coating containing amorphous silicon, wherein the patterned coating is over the conductive layer and the patterned coating is in electrical communication with the conductive layer.
A further aspect of the invention provides a calibration standard for an SEM system including means for providing sub-micron amorphous silicon features having smooth surfaces and means for grounding the amorphous silicon features during the calibration scanning.
A further aspect of the invention provides a package including contents including a silicon wafer and a patterned coating over the silicon wafer containing amorphous silicon, and instructions for using the contents as a calibration standard for an SEM system.
A further aspect of the invention provides a method of calibrating an SEM system including obtaining a calibration measurement by employing the SEM system to measure a dimension of a feature of a calibration standard including a patterned coating containing amorphous silicon and using the calibration measurement to calibrate the SEM system.
A further aspect of the invention provides an SEM system including a scanning electron microscope and a calibration standard including a pattern formed of an amorphous material containing amorphous silicon, wherein the SEM system is configured to employ the calibration standard in calibrating the scanning electron microscope.
REFERENCES:
patent: 5625170 (1997-04-01), Poris
patent: 5920067 (1999-07-01), Cresswell et al.
patent: 5989969 (1999-11-01), Watanabe et al.
patent: 6016684 (2000-01-01), Scheer et al.
patent: 6048743 (200
Choo Bryan K.
Phan Khoi A.
Rangarajan Bharath
Singh Bhanwar
Subramanian Ramkumar
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Font Frank G.
Nguyen Sang H.
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