Graduated delay line for increased clock skew correction...

Details Graduated delay line for increased clock skew correction... Graduated delay line for increased clock skew correction...

2005-05-19

2008-12-30

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S149000

Reexamination Certificate

active

07471130

ABSTRACT:
Clock synchronization and skew adjustment circuits are described that utilize varying unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement, allowing a reduced circuit implementation and improved lock characteristics. These graduated or a stepped unit time delays allow reduction in the number of the fine unit delay elements of the delay lines by placing a fine delay element granularity at the most critical timings to sense and adjust for the portion of the clock signal time period that are high speed or critical. This allows clock synchronization and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size and power consumption, while having improved lock characteristics over a wide range of frequencies.

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