Graded sealing systems for semiconductor package

Details Graded sealing systems for semiconductor package Graded sealing systems for semiconductor package

1985-07-08

1987-11-03

James, Andrew J.

357 73, 357 67, H01L 2302, H01L 2306, H01L 2310, H01L 2348

Patent

active

047046260

ABSTRACT:
A graded seal assembly adapted for hermetically sealing a semiconductor package is disclosed. First and second members having first and second coefficients of thermal expansion respectively are provided. A leadframe is disposed between the first and second members. A first sealing glass is bonded to opposite surfaces of the leadframe and is disposed between the leadframe and the first member for sealing the leadframe to the first member. The second sealing glass is bonded to the second member. The second sealing glass has a third CTE which has a mismatch of less than about 5.times.10.sup.-7 in/in/.degree.C. with said second member. A graded interface zone having stratified layers fuses the first and second sealing glasses. Each of the layers in the zone has a coefficient of thermal expansion which is mismatched less than about 5.times.10.sup.-7 in/in/.degree.C. with an adjacent layer to absorb thermal stress formed by exposure of the semiconductor package to thermal cycling.

REFERENCES:
patent: 3340347 (1967-09-01), Spiegler
patent: 3404319 (1968-10-01), Tsuji et al.
patent: 3937638 (1976-02-01), Plewes
patent: 4135038 (1979-01-01), Takami et al.
patent: 4434016 (1984-02-01), Saleh et al.
patent: 4524238 (1985-06-01), Butt
patent: 4542259 (1985-09-01), Butt
"Metal Circuit Board Substrates for Direct Mounting of Ceramic Chip Carriers" by Dance et al., in the First Annual Conference of the Internation Electronics Packaging Society on Nov. 9-10, 1981.

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