Metal fusion bonding – Process – Metal to nonmetal with separate metallic filler
Patent
1988-07-14
1989-10-24
Godici, Nicholas P.
Metal fusion bonding
Process
Metal to nonmetal with separate metallic filler
2281802, 228254, 22826312, 357 67, 357 71, B23K 3102, H01L 2348, H01L 2954
Patent
active
048756172
ABSTRACT:
A bonding structure of gold-tin (80:20) eutectic bonding of two gold layers on an integrated circuit chip and a substrate carrier, such as a tape in a tape automated bonding (TAB) process, is provided. A method provides gold-tin eutectic bumps on an integrated circit wafer or on the tape or other substrate carrier. The quantity of tin reacting with gold in the method is limited and controlled, allowing gold consumption to be reduced by an order of magnitude. A first layer of gold is provided on bonding pads of the wafer after formation of the integrated circuits. A layer of tin is formed on the first gold layer. The first gold and tin layers are thermally treated at a temperature above 280.degree. C. to form gold-tin substantially eutectic bumps on the first gold layer. A second gold layer is provided as spots on the tape or other substrate carrier. The second gold layer has a thickness of at least about 5 percent of the gold rich eutectic body. After dicing the wafer into individual integrated circuit chips, the eutectic body on the chip's pads is placed on and bonded to the second gold layer by heating to a temperature greater than the temperature of the previous thermal treatment and leaving unalloyed gold in the first and second gold layers. The eutectic bumps can alternatively be made on the tape, with a thin gold layer on the wafer. The eutectic bumps can also be deposited directly as the gold-tin eutectic. The gold, tin or eutectic layers can be plated, sputtered, evaporated with or without use of a mask or photolithography, screened, chemical vapor deposited, or any combination of these techniques. The resulting structure has increased reliability, especially for on board application at elevated temperatures, due to avoiding brittle intermetallics. The method and structure allows smaller bonding pads to be used on integrated circuit chips, giving smaller chips with higher yields.
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Godici Nicholas P.
Heinrich Samuel M.
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