Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2003-03-07
2004-03-02
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S767000, C257S768000, C257S780000, C438S611000, C148S430000, C148S678000
Reexamination Certificate
active
06700199
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bonding wire for electrically connecting a semiconductor chip and a lead frame or a printed circuit board (PCB) in a packaging process, and more particularly, to a bonding wire which does not cause chip cracks because it forms a soft ball.
2. Description of the Related Art
Referring to
FIG. 1
, a general semiconductor package includes a semiconductor chip
10
on a pad
50
, a plurality of chip pads
20
formed on the semiconductor chip
10
as input/output ports for a variety of signals, a plurality of lead frames
40
electrically connected to the semiconductor chip
10
to receive the variety of signals from or to output the same to an external circuit; and a bonding wire
30
for electrically connecting the chip pad
20
and the lead frame
40
. This structure of the general semiconductor package is protected by, for example, epoxy molding compound resin.
One end of the bonding wire
30
bound to the chip pad
20
includes a compressed ball
32
and a neck
34
as a connector between the compressed ball
32
and the bonding wire
30
. In a wire bonding process, one end of the bonding wire
30
is melted by discharging to form a free air ball of a predetermined size and pressed on the chip pad
20
to be bound to the chip pad
20
. A loop of the bonding wire
30
having an appropriate height and length is formed to reach a corresponding lead frame
40
, and the other end of the bonding wire
30
is bound to the lead frame
40
with an application of pressure. As a result, the semiconductor chip
10
and the lead frame
40
are electrically connected.
A gold-silver (Au-Ag) alloy is typically used for the bonding wire
30
. Silver forms a complete solid solution together with gold, so the alloy can be produced on a large scale, thereby lowering the manufacturing cost of the bonding wire. However, when a loop is formed with the conventional bonding wire
30
, the bonding wire
30
often breaks near the neck
53
, as indicated by reference numeral
35
. A reduced loop height due to the increasing integration density of a semiconductor device further increases the breakage
35
of the neck
34
. The breakage
35
occurs due to a poor tensile strength of the bonding wire
30
. Accordingly, a signal transmission path formed by the loop is opened. In addition, the poor strength of the bonding wire
30
causes a loop sagging or sweeping (indicated by reference numeral
36
) in a molding process, so that adjacent loops contact one another.
Examples of research on the conventional Au-Ag bonding wire are in Japanese Laid-open Application Nos. 1998-326803, 1999-6781 1, and 1999-67812. According to the disclosures, to increase the bonding strength and to reduce the sweeping of the Au-Ag bonding wire in the molding process, cupper (Cu), palladium (Pd), or platinum (Pt) was added in an amount of 0.01-4% by weight, and at least one of calcium (Ca), beryllium (Be), and indium (In) was added in an amount of 0.0005-0.05% by weight. Japanese Laid-open Patent Application No. 2000-150562 disclosed that the addition of at least one of Pd, titanium (Ti), Ca, Be and lanthanum (La) in an amount of several parts per million to several percentages by weight results in a ball grain refinement and increases bonding strength after high-temperature heating.
However, the conventional techniques were inclined to increasing the bonding strength and reliability and to preventing the sweeping of the bonding wire in the molding process, ignoring a crucial chip crack due to the inherently hard ball of the Au-Ag alloy. In addition, the problem of the breakage occurring near the ball neck in the loop formation remains unsolved. Furthermore, the ball grain refinement in Japanese Laid-open Patent Application No. 2000-150562 increases the area of grain boundaries acting as Au and Ag atom diffusion paths, and thus it is likely to lower reliability.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a highly reliable bonding wire which has a strong tensile strength at both room temperature and high-temperature and causes no chip crack in a wire bonding process and no rupture of a ball neck when the bonding wire is looped.
In one aspect, the present invention provides a bonding wire for a semiconductor device, containing: a Au-Ag alloy including about 5-40% Ag by weight in Au having a purity of 99.999% or greater; at least one element of a first group consisting of Pd, Rh, Pt, and Ir in an amount of about 50-10,000 ppm by weight; at least one element of a second group consisting of B, Be, and Ca in an amount of about 1-50 ppm by weight; at least one element of a third group consisting of P, Sb, and Bi in an amount of about 1-50 ppm by weight; and at least one element of a fourth group consisting of Mg, TI, Zn, and Sn in an amount of about 5-50 ppm by weight. In the bonding wire according to the present invention, as many kinds of elements as possible from each of the first through fourth groups are added for synergism.
In the specification, the amounts of elements are expressed in ppm by weight and % by weight based on the total weight of the bonding wire.
REFERENCES:
patent: 5702814 (1997-12-01), Hanada et al.
patent: 5989364 (1999-11-01), Kitamura
patent: 6103025 (2000-08-01), Herklotz et al.
patent: 6150262 (2000-11-01), Go et al.
Cho Jong-Soo
Joung Dong-Ho
Moon Jeong-Tak
Lee Calvin
MK Electron Co., Ltd.
Volpe and Koenig P.C.
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