Gold code generator design

Details Gold code generator design Gold code generator design

2006-07-18

2006-07-18

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S253000, C708S254000

Reexamination Certificate

active

07080107

ABSTRACT:
A gold code generator is described comprising two pairs of linear feedback shift registers, the seed values for the second pair of linear feedback shift registers are different from the seed values for the first pair of linear feedback shift registers. The second seed values are calculated from the first seed values. The use of this second pair of linear feedback shift registers prevents the need to use a wide span of taps to the linear feedback shift register to produce output bits. By using two pairs of linear feedback shift registers, a parallel output implementation can be produced in which multiple output bits are produced in a single clock cycle.

REFERENCES:
patent: 5111416 (1992-05-01), Harada
patent: 5566099 (1996-10-01), Shimada
patent: 6192385 (2001-02-01), Shimada
patent: 2001/0033663 (2001-10-01), Ishimoto et al.

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