Global planarization using SOG and CMP

Details Global planarization using SOG and CMP Global planarization using SOG and CMP

1995-12-05

2000-01-04

Kunemund, Robert

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

438388, 438111, 438390, 438691, H01L 2120

Patent

active

060109637

ABSTRACT:
A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.

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