Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-10-25
2001-03-13
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S672000, C438S706000, C438S723000, C438S724000, C438S734000
Reexamination Certificate
active
06200898
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to achieve global planarization for integrated circuits comprised with dynamic random access memory, (DRAM), devices, and with logic devices.
(2) Description of Prior Art
Integration of memory devices, such as DRAM devices, with logic devices, on the same semiconductor chip, have resulted in enhanced performance, as well as cost reductions, for the specific semiconductor chip formed with both type devices, when compared to counterpart combinations of semiconductor chips, each comprised with either only memory or only logic devices. In addition, the performance of DRAM devices has been enhanced via the use of crown shaped capacitor structures, resulting in increased capacitor surface area, thus supplying increased capacitance and signal. However the high step height of the DRAM, crown shaped capacitor, located in a memory cell array, adjacent to peripheral regions comprised with lower step height, logic devices, can lead to difficulties when attempting to globally cover these devices with insulator.
This invention will describe a novel procedure for obtaining global planarization for semiconductor chips comprised with both type devices, resulting in a smooth top surface topography for passivating insulator layers which overlay both DRAM devices, comprised with crown shaped capacitor structures, and logic devices, comprised with metal interconnect structures, less demanding in step height than the crown shaped capacitor structures, of the DRAM devices. This is accomplished using a series of selective HF vapor etch procedures. After formation of the crown shaped storage node structures, in storage node openings formed in a thick borophosphosilicate glass, (BPSG), layer, a thin, chemically vapor deposited, silicon oxide layer, formed using tetraethylorthosilicate, (TEOS), as a source, is used to cover the crown shaped storage node structures, as well as covering all regions of the top surface of the BPSG layer, including the region between crown capacitor shapes. A photoresist shape is formed overlying non-crown shaped structures, followed by a first HF vapor etch procedure, selectively removing the TEOS formed, silicon oxide layer from the crown capacitor shapes, as well as from the BPSG layer, located between the crown shaped structures. A second HF vapor etch is then used to remove the BPSG layer from between crown shaped structures, using either the photoresist shape as a mask, or removing the photoresist shape, and using the thin TEOS formed, silicon oxide layer, as an etch mask. The use of the TEOS formed silicon oxide layer, and the selective HF vapor etch, do not rely on the photoresist shape, which can be damaged during a conventional wet etch, BPSG removal procedure, to protect insulator layers overlying non-DRAM regions. Subsequent formation of polysilicon upper plate structures, fill the space between the crown shaped structures, resulting in a smooth top surface topography for a semiconductor device, comprised with high step height, DRAM devices, and with less severe step height, logic devices.
Prior art, such as Kleinhenz et al, in US. Pat. No. 5,876,879, as well as Man, in U.S. Pat. No. 5,376,233, describe methods of selectively etching insulator layers, using HF vapor etching. These prior arts however, do not describe the novel series of procedures, photoresist masking, TEOS formed silicon oxide masking, and the selective HF vapor etch, used in this invention, to obtain global planarization for semiconductor chips comprised with varying step height structures.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a smooth top surface topography for a semiconductor chip comprised with DRAM devices, featuring high step height features, such as crown shaped capacitor structures, and comprised of logic devices, in peripheral regions of the semiconductor chip.
It is another object of this invention to protect insulator layers located overlying peripheral regions of the semiconductor chip, from procedures used to remove insulator material from between DRAM crown shaped structures, via use of photoresist masking shapes, and via the use of a thin silicon oxide layer, formed using TEOS as a source.
It as yet another object of this invention to use a first HF vapor etching procedure, to selectively remove the TEOS deposited, silicon oxide layer, from an underlying borophosphosilicate glass, (BPSG), layer, using a photoresist shape as a mask, and to use a second HF vapor etching procedure, to selectively etch a region of the BPSG layer, using the photoresist shape, or the TEOS deposited silicon oxide layer, as a mask.
In accordance with the present invention a method of achieving global planarization for a semiconductor chip, comprised with DRAM cell arrays, and peripheral logic devices, featuring the use of TEOS deposited silicon oxide masking, and selective HF vapor etching procedures, is described. After forming openings in a BPSG layer, polysilicon crown shaped storage node shapes are formed in these openings, overlying and contacting, conductive plug structures, which in turn are used to communicate with underlying source/drain regions, of a transfer gate transistor. A thin, TEOS deposited, silicon oxide layer, is then formed overlying the BPSG layer, and covering the polysilicon crown shape storage node structures. A photoresist shape is used as a mask to protect the thin, TEOS formed, silicon oxide layer, overlying peripheral logic device regions, during a first, selective HF vapor etch procedure, used to remove the thin, TEOS formed, silicon oxide layer, from the top surface of the BPSG layer, located between polysilicon crown shaped storage node structures, as well as removing the thin, TEOS layer from the surface of the polysilicon crown shaped storage node structures. The photoresist shape, can remain, or be removed, prior to a second, selective HF vapor procedure, used to selectively remove unprotected regions of the BPSG layer, in an area between polysilicon crown shaped storage node structures, with the photoresist shape, or the thin, TEOS layer, providing the desired masking needs. After formation of a capacitor dielectric layer, on the exposed surfaces of the polysilicon crown shaped capacitor structures, a polysilicon layer is deposited, filling the space between the polysilicon crown shaped capacitor structures. A patterning procedure, used to define a polysilicon upper plate structure, completes the fabrication procedure of the crown shaped capacitor structure, encased with the BPSG layer, resulting in a semiconductor chip exhibiting a top surface topography, featuring a top surface of the crown shaped capacitor structures, at the same level as a top surface of the BPSG layer, located overlying peripheral logic device regions.
REFERENCES:
patent: 5376233 (1994-12-01), Man
patent: 5876879 (1999-03-01), Kleinhenz et al.
patent: 6074955 (2000-06-01), Lin et al.
patent: 6136661 (2000-10-01), Yen et al.
patent: 6136716 (2000-10-01), Tu
Ackerman Stephen B.
Powell William
Saile George O.
Vanguard International Semiconductor Corporation
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