Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-03-15
2002-11-12
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185130, C365S185180, C365S185280
Reexamination Certificate
active
06480417
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains generally to computers. In particular, it pertains to computer memory circuitry.
2. Description of the Related Art
Flash memory is a type of rewritable memory that stores data in each cell by charging up a floating transistor gate to a predetermined charge level, which the transistor can then retain for an extended period of time. Each cell, which can be represented by a single transistor, can be 1) programmed (written) by charging up the floating gate of the transistor to a predetermined level, 2) read by sensing the amount of stored charge in the floating gate, and 3) erased by draining the stored charge from the transistor. Each of these functions requires a different set of bias voltage on the transistor. As an example, one type of flash memory requires voltages on the gate/source/drain, respectively, of approximately 10/0/5 for programming, −9/0/0 for erasing, and 5/0/1 for reading.
To save valuable space on the die, large numbers of these cells have common connections so that a single voltage line may connect multiple gates, another single voltage line may connect multiple drains, and another single voltage line may connect multiple sources. Each of these groups of connections can then be serviced by a single, switchable voltage supply, so that all common connections in a group can have the same bias voltage and the entire group of cells can be biased for the same function of program, read, or erase. By connecting these common voltage lines in a column/row matrix, individual cells can be addressed, while still minimizing the amount of die space devoted to these interconnections.
FIG. 1
shows an example of six memory cells
2
-
7
, which can be a small subset of a much larger block of thousands of cells. The sources of all six are connected together by a common source line
14
, which can supply a common source voltage to all six cells. The gates of cells
2
-
4
are connected to one common gate line
11
, while the gates of cells
5
-
7
are connected to another common gate line
12
, so that either cells
2
-
4
or cells
5
-
7
can be selected by placing the proper voltage on one of these common gate lines. The drains of cells
2
,
5
are likewise connected to one common drain line
15
, cells
3
,
6
to a second common drain line
16
, and cells
4
,
7
to a third common drain line
17
. To select a single cell, the source, gate, and drain lines to that particular cell are activated. For example, by placing proper read voltages on source line
14
, gate line
11
, and drain line
16
, only cell
3
would have all the proper bias voltage for reading, and any value detected during the read operation would be attributed to cell
3
.
Due to the preferred method of organizing cells, the common gate lines are typically referred to as wordlines, and the common drain lines are typically referred to as bitlines. A typical memory may have many cells grouped together in a block in the manner described. For example, in a flash memory, each wordline may be connected to 512 cells, and each bitline may be connected to 1024 cells, for a total of over 0.5 million cells per block, with eight blocks in a plane. Multiple planes can be combined into a memory array. The array, plane, block, word, and bit numbers can be decoded from a memory address to select the particular cell that is being addressed.
Global voltage lines are typically switched on or off separately to each array, so that cells in each array can be programmed, read, or erased independently of the other arrays. However, within each array, all planes may be required to perform the same function if the cells in those arrays are addressed at the same time, due to their common global voltage line.
FIG. 2
shows a conventional bitline selection circuit for an array
20
, in which a switch or multiplexer
21
can switch the drain voltage for either a read operation (read voltage VR), or a program operation (program voltage VP) to array
20
. Within the array, transistor switch
22
can connect that voltage to global bitline GBL, or disconnect it if that voltage is not needed in the array at that time. Since the same global bitline goes to multiple planes and to all blocks
0
,
1
,
2
, etc., within those planes, these planes and blocks are all simultaneously biased for only one of the functions of program, read, and erase. Within Block
0
, transistors
26
-
0
,
1
,
2
,
3
(through
26
-
n
, where n is the highest-numbered bitline) can direct that voltage to any of local bitlines LBL
1
,
2
,
3
, etc., where the voltage can be provided to any of the memory cells
29
-
x
(only one cell is shown in the drawing for clarity) that are connected to that bitline and that are selected by the appropriate wordline (not shown in FIG.
2
). Bitlines
15
-
17
in
FIG. 1
can be considered local bitlines. At the same time, each of Blocks
1
,
2
, etc. will have their own equivalent of transistors
26
-
0
,
1
,
2
, etc., so that each block can simultaneously select a different local bitline, and therefore a different memory cell.
This conventional addressing scheme prevents memory cells in the same array from performing different operations at the same time, since the global bitline provides the same bitline bias voltage to the blocks and planes within an array. Thus a read-while-write function (read one cell while programming another) cannot be performed unless the read and write operations take place in different arrays, with each array typically representing 10's of megabits of addressable memory.
REFERENCES:
patent: 5847994 (1998-12-01), Motoshima et al.
patent: 5894437 (1999-04-01), Pellegrini
patent: 5978264 (1999-11-01), Onakado et al.
patent: 6016270 (2000-01-01), Thummalapally et al.
Blakley Sokoloff Taylor & Zafman LLP
Intel Corporation
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