Television – Video display – Projection device
Reexamination Certificate
1998-06-02
2001-05-01
Faile, Andrew I. (Department: 2711)
Television
Video display
Projection device
C348S148000, C348S771000, C358S461000, C345S085000, C345S156000
Reexamination Certificate
active
06226054
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to digital video display systems, and more particularly to digital display systems utilizing bit-planes for performing pulse width modulation to display digital video data.
BACKGROUND OF THE INVENTION
Binary spatial light modulators are typically comprised of an array of elements each having two states, on and off. The use of pulse width modulation (PWM) is one conventional approach of digitally displaying incoming analog video data, as compared to an analog display such as a cathode ray tube (CRT) based system. PWM typically comprises dividing a frame of incoming video data into weighted segments. For example, for a system that samples the luminance component of incoming video data in 8-bit samples, the video frame time is divided up into 255 time segments or pixel values (2
8
−1). Conventionally, the 8-bit samples are formatted with binary values. The most significant bit (MSB) data is displayed on a given element for 128 time segments. In the present example, the next MSB has a time period of 64 time segments, and so on, such that the next bits have weights of 32, 16, 8, 4, 2 and 1 time segments, consecutively. Thus, the least significant bit (LSB) has only one time segment. All pixel values are comprised of a summation of these weighted bits.
In DMD display systems, such as disclosed in commonly assigned U.S. Pat. No. 5,278,652 entitled “DMD Architecture and Timing for Use in a Pulse-Width Modulated Display System”, the teachings of which are incorporated herein by reference, light intensity for each pixel is typically displayed as a linear function of the pixel digital codes. For an 8-bit binary code, 0 is no light, 255 is peak light, and 128 is midscale light. Codes between 0 and 255 form a grayscale in each color. This grayscale sets the image resolution for the system by defining the number of discrete levels of light that can be produced for each color; i.e. red, green and blue.
Pulse width modulation (PWM) schemes for controlling the mirrors conventionally modulate the mirrors with time periods being powers of two. For example, 20 us, 40 us, 80 us, 160 us, 320 us, 640 us, 1280 us, and 2,560 us are used to define the mirror on-times for the 8 bit-planes needed for 8-bit video where 5.5 ms is available per color of light being modulated.
Light is transmitted to the image plane, such as a display screen, as black for the bit-plane of a pixel which is logic 0 or at full brightness during a bit-plane which equals logic 1. Since the on-times for bit-planes vary, this results in PWM over a frame period. The viewer's eyes integrate the on-times of modulated light so that gray levels are perceived.
A typical DMD has a memory cell under each mirror that contains the bit-plane of data to be applied to that mirror. In every video frame, each bit-plane of data is first loaded into the memory cells of the DMD, one bit-plane at a time, and then the bit-plane data in the memory cells under the mirrors are globally applied to all associated mirrors at the same time. This global application of data to all mirrors at the same time is called “global-reset” operation of a DMD. A DMD loaded and operated in a global-reset mode requires that all DMD memory cells be loaded before data is globally applied to the mirrors. In the case of bit-planes representing LSBs with short on-times, data is successfully applied to the mirrors and displayed, but then all the mirrors are reset to the off-state prior to a new bit-plane being completely loaded into the memory cells of the DMD. This is because a new bit-plane load can not completely take place in the background while displaying the short bit on-times. All memory cells must be cleared (via a high speed parallel clear of all memory cells) prior to the end of the short bit on-times. The clearing of the entire memory is needed so that all mirrors can be turned off globally to terminate the short on-times. However, the mirrors can not be turned back on until the DMD is fully loaded with a new bit-plane of data. This results in “deadtime” after displaying any LSB bit-planes with on-times less than the DMD bit-plane data load time.
FIG. 1
shows an example of light loss due to deadtimes after the lower weighted bit-planes are displayed. For example, consider bit-plane B
3
. B
3
has an on-time of 160 us, but the DMD load time is 200 us, and thus another bit-plane can not be loaded in the background while bit plane B
3
is being displayed. Thus, the DMD will have all mirrors off for 200 us after each 160 us on-time for bit-plane B
3
to load a split B
7
bit-plane, creating the deadtime and consequently a significant light loss.
Thus, any time a bit-plane on-time is less than the DMD load time, i.e. B
0
, B
1
, B
2
and B
3
, a 200 us deadtime will result after that bit-plane is displayed on the DMD, -where only two deadtimes can be hidden behind spokes of the colorwheel in one DMD system. This results in lost light on the display screen since all mirrors are turned off during this deadtime.
The following is an example of the total light loss for an 8-bit color sequential DMD system, using a 6 segment color wheel with 2 segments each of red, green and blue (RGB);
Bit
Deadtime (per color)
B7
0
B6
0
B5
0
B4
0
B3
200 us
B2
0 (200 us hidden behind spoke 1)
B1
200 us
B0
0 (200 us hidden behind spoke 2)
For a 6-segment RGB color wheel, 3× (200 us×2)=1200 us of deadtime exists during each 16.67 ms video frame. (The two other deadtimes, for bit-plane B
0
and B
2
for each color will be hidden in the color wheel spokes, thus, no light is lost due to these bits due to short load times). When including spoke losses, the effective video frame is typically 12.33 ms. The equation for determining the total lost light is then:
100−((12.33 ms−1.2 ms)×100)/12.33 ms=~10% light loss
There is a need to provide a means to regain this lost light while using the global-reset approach. The present invention seeks to eliminate all the deadtimes not hidden by spokes, and increase lumens to the display screen. The present invention also sets forth to reduce the number of bit-planes required for displaying the digital video data, without sacrificing the total number of grayshades per color.
SUMMARY OF THE INVENTION
The present invention achieves technical advantages as a method of displaying digital video data using pulse width modulation by using spatial-temporal multiplexing of two bit-planes. One bit-plane is eliminated, and two other bit-planes are re-weighted to maintain, for instance, 8-bits of resolution per color while using only 7 bit-planes. One deadtime is eliminated since one of the lower-weighted bit-planes is eliminated, and another deadtime is eliminated because another shorter bit-plane weight is increased sufficiently that no DMD memory clear function is needed to show the short bit on-time.
In a first preferred embodiment, the lowest weighted bit-plane B
0
is eliminated, and the bit-plane B
2
is increased and reweighted from 4 to 6. In a second preferred embodiment, the second lowest weighted bit-plane B
1
is eliminated, and the bit-plane B
3
is reweighted from 8 to 12. In both preferred approaches, digital logic is applied to two of the processing bits for each pixel prior to formatting the incoming video data into the displayed bit-planes. Spatial-temporal multiplexing is performed on the two bits to achieve grayscales of the incoming video data. Each of these two bits are ternary. A two-frame spatial-temporal pattern, such as a checkerboard, is used on these bits to avoid spatial and temporal contouring and to form the grayshades. For a given source pixel value to be displayed, depending on the value, spatial-temporal multiplexing is performed using two bits over two consecutive video frames. For instance, according to the first preferred embodiment of the present invention where the B
0
bit-plane is eliminated and the bit-plane B
2
is reweighted from 4 to 6, a pixel value of 4 is perceived by displaying a pixel value 6 for one frame, an
Hewlett Gregory J.
Morgan Daniel J.
Vankessel Peter F.
Brady III Wade James
Faile Andrew I.
Huang Sam
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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