Pulse or digital communications – Pulse position – frequency – or spacing modulation
Reexamination Certificate
2007-02-07
2010-11-30
Ghayour, Mohammad H (Department: 2611)
Pulse or digital communications
Pulse position, frequency, or spacing modulation
C343S853000, C343S850000, C343S852000, C343S858000, C343S859000, C343S860000, C343S861000, C370S213000
Reexamination Certificate
active
07843992
ABSTRACT:
In one embodiment, a circuit is provided that includes: an impulse generator operable to provide a pulse train; a pulse position modulator having a splitting junction configured to receive the pulse train, the pulse position modulator including a plurality of n transmission lines, wherein n is an integer, the n transmission lines being selectably coupled in parallel between the splitting junction and a combining junction, the impulse generator driving each transmission line having a unique delay such that if the transmission line is selected, each pulse received at the splitting junction is uniquely delayed into a delayed pulse, whereby if all the transmission lines are selected, each pulse received at the splitting junction is uniquely delayed into a corresponding plurality of n delayed pulses; and a controller operable to select the transmission lines responsive to received words of n bits in length, each word arranged from a first bit to an nth bit, and wherein the transmission lines are arranged from a first transmission line to an nth transmission line corresponding to the bits in the received words such that a given bit in a received word controls the selection of the corresponding transmission line.
REFERENCES:
patent: 6515622 (2003-02-01), Izadpanah et al.
patent: 7283595 (2007-10-01), Jun
patent: 7312763 (2007-12-01), Mohamadi
patent: 7394866 (2008-07-01), McCorkle
patent: 7683852 (2010-03-01), Mohamadi
patent: 2003/0161411 (2003-08-01), McCorkle et al.
patent: 2004/0160293 (2004-08-01), Ko et al.
patent: 2005/0075080 (2005-04-01), Zhang
patent: 2006/0039449 (2006-02-01), Fontana et al.
patent: 2008/0130685 (2008-06-01), Rogerson et al.
patent: 2008/0252546 (2008-10-01), Mohamadi
Poulton, J. et al., A Tracking Clock Recovery Receiver for 4Gb/s Signaling, Hot Interconnects V Symposium Record, Aug. 1997, p. 157-169, Stanford.
Farjad-Rad, R., et al., An Equalization Scheme for 10Gb/s 4-PAM Signaling Over Long Cables, Mixed Signal Conference, Jul. 1997, Cancun, Mexico.
Widmer, A.X. et al., Single-chip 4*500-MBd CMOS Transceiver, IEEE Journal of Solid-State Circuits, Dec. 1996, p. 2004-2014, vol. 31, No. 12.
Fiedler, A. et al., A 1.0625 Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-emphasis, IEEE International Solid-State Circuits Conference, 1997, p. 238-239.
Dally, W.J. et al., Transmitter Equalization for 4-Gbps Signaling,.IEEE Micro, Jan.-Feb. 1997, p. 48-56, vol. 16 No. 1.
Kim, S., B. Lee, D. Neikirk, Compact Equivalent Circuit Models for the Skin Effect, http://weewave.mer.utexas.edu/, 1996, University of Texas at Austin.
Yukawa, A. et al., A CMOS 8-bit High Speed A/D Converter IC, Proceedings of the Tenth European Solid-State Circuits Conference, Jun. 1985, p. 193-196.
Farrokh Mohamadi, http://grouper.ieee.org/groups/802/3/ae/public/may00/mohamadi—1—0500.pdf, IEEE meeting, May 2000.
M.M. Green, et al., OC-192 Transmitter in Standard 0.18u-m CMOS, ISSCC Digest of Technical Papers, 2002, p. 248-249.
J. Zerbe, et al., A 2Gb/s/pin 4-PAM Parallel Bus Interface with Crosstalk Cancellation, Equalization, and Integrating Receivers, ISSCC Digest of Technical Papers, 2001, p. 66-67.
R. Farjad-Rad et al., IEEE J. Solid-State Circuits, May 2000, p. 757-764, vol. 35.
C.K. Yang et al., A Serial-Link Tranceiver Based on 8-G Samples/s A/D and D/A Converters in .25-um CMOS, IEEE J. Solid State Circuits, Nov. 2001, p. 1684-1692, vol. 36.
K. Chang, et al., A .4-4Gbb/s CMOS Quad Tranceiver Cell Using On-Chip Regulated Dual-Loop PLLs, 2002 Symposium on VLSI Circuits Digest of Technical Papers, p. 88-91.
SDMG13, 3 Gbits/s-6.25 Gbits Serializer/Deserializer, Data Sheet, Agere Corporation, May 2003.
J. Zerbe, et al., Equalization and Clock Recovery for a 2.5-10Gbs 2-PAM/4-PAM Backplane, ISSCC 2003, Paper 4.6.
C. Mick, http://grouper.ieee.org/groups/802/3/tutorial/march98/mick—170398.pdf, IEEE meeting, Mar. 1998.
http://www.ieee802.org/802—tutorials
ov03/10GBASE-T%20tutorial.pdf, IEEE Meeting, Nov. 2003.
B. Jones, http://grouper.ieee.org/groups/802/3/10GBT/public/jan03/ jones—2—0103.pdf, IEEE Meeting, Jan. 2003.
Farrokh Mohamadi, Critical Data Timing in Distributed Systems, Defense Electronics, May 2004, p. 13-18.
Farrokh Mohamadi, Si Integration with Millimeter Wave Phased Array Antenna, RF Design, Feb. 2004, p. 40-48.
Ghayour Mohammad H
Giles Eboni
Haynes & Boone LLP.
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