Global event qualification system

Details Global event qualification system Global event qualification system

1987-11-05

1989-08-15

Eisenzopf, Reinhard J.

Electricity: measuring and testing

Plural, automatically sequential tests

371 15, G01R 3100

Patent

active

048578355

ABSTRACT:
Test logic may be included in the design of an integrated circuit (IC) to facilitate testability. In most instances, an IC's test logic can only be activated while the IC, or logic sections within the IC, are placed in a non-functional test mode. The present invention is directed toward an event qualification structure providing the timing and control required to activate an IC's test logic during normal functional operation.

REFERENCES:
patent: 4023142 (1977-05-01), Woessner
patent: 4513418 (1985-04-01), Bardell et al.

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