Global erase/program verification apparatus and method

Details Global erase/program verification apparatus and method Global erase/program verification apparatus and method

1999-10-06

2001-01-30

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S185290

Reexamination Certificate

active

06181605

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed to a memory system and more particularly to an apparatus and method to verify whether multiple memory cells have successfully programmed or erased.
RELATED ART
FIG. 1
illustrates a cross sectional view of a conventional memory transistor, also known as a memory cell. The memory transistor includes a control gate CG, a floating gate FG, a drain D, a source S, and a well W. Thin oxide layers isolate the floating gate FG from the control gate CG as well as the well W.
FIG. 2
schematically illustrates a conventional NAND type flash memory array
100
that includes numerous memory cells, each depicted in
FIG. 1. A
“string” includes a selection transistor T
i−1
, memory transistors M
i−1
to M
i−j
, and a selection transistor T
i−2
, all being serially coupled. Each string can be coupled to a bit line BLj and a common source CS through selection transistors T
i−1
and T
i−2
, respectively. The control gates for selection transistors T
i−1
and T
i−2
are respectively connected to selection lines Sl
1
and Sl
2
. The control gates for the memory transistors M
i−1
to M
i−j
are respectively connected to word lines W
1
to W
j
. Typically, a read operation is performed on a page basis, i.e., flash memory cells coupled to a word line are read together.
Herein, a memory transistor represents logical LOW when it is programmed to have a threshold voltage that is larger than a predetermined minimum threshold voltage for logical LOW bits. Correspondingly, a memory transistor represents a logical HIGH when it is erased to have a threshold voltage that is less than a predetermined maximum threshold voltage for logical HIGH bits. One skilled in the art will understand that logic level assignments to the predetermined minimum and maximum threshold voltages are arbitrary.
During testing of memory cells and subsequent consumer use of memory cells, it is desirable to speed the time to determine the success of both program and erase operations. Thus what is needed is a method and apparatus to verify successful program and erase operations.
SUMMARY
An embodiment of the present invention includes a verification circuit that determines whether a plurality of memory cells are programmed, where each memory cell has an associated data latch that identifies whether the cell is to be programmed, the verification circuit including a plurality of switches, each switch being coupled to a data latch, where each switch is controlled by the state of the associated data latch, where if all memory cells identified to be programmed are programmed, the state of all switches are the same.
An embodiment of the present invention includes a verification circuit that determines whether a plurality of memory cells are erased, the verification circuit including a plurality of switches, each switch being coupled to measure the state of an associated memory cell, where the state of all switches are the same if all memory cells are erased.
Advantageously, only a single output needs to be measured in a program or erase verification thereby decreasing the time needed to erase or program verify.
Various embodiments of the present invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.


REFERENCES:
patent: 5936890 (1999-08-01), Yeom
patent: 6009014 (1999-12-01), Hollmer et al.
patent: 6009015 (1999-12-01), Sugiyama
patent: 6055188 (2000-04-01), Takeuchi et al.
patent: 6055189 (2000-04-01), Ogane

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