Global clock tree de-skew

Details Global clock tree de-skew Global clock tree de-skew

2002-04-09

2004-06-01

Nguyen, Linh M. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

06744293

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to digital communications, and more particularly to a delay lock (DLL) circuit for de-skewing a global clock tree.
The circuits which comprise a digital device usually operate under control of a clock signal. When coordination and synchronization are required, it is disadvantageous for each circuit to operate under its own local clock signal. For proper synchronization, a global clock tree is sometimes used, in which a global clock signal is distributed to various locations on a chip for local clock control.
Unfortunately, the global clock signal may become skewed from its original form by the time it arrives at a certain location on the chip or in a system. For instance, a long wire routing of the global clock signal may introduce delay into the signal. Or, the global clock tree may suffer from insertion delay on one or more of its clock branches. The problem of clock skew is exacerbated at higher clock speeds for faster processing.


REFERENCES:
patent: 5552727 (1996-09-01), Nakao
patent: 5629651 (1997-05-01), Mizuno
patent: 5822573 (1998-10-01), Saeki et al.
patent: 5994934 (1999-11-01), Yoshimura et al.
patent: 6437616 (2002-08-01), Antone et al.

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