Glitchless clock selection circuit using phase detection...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – Having selection between plural continuous waveforms

Reexamination Certificate

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Details

C327S144000, C327S407000

Reexamination Certificate

active

07071738

ABSTRACT:
A clock selection circuit includes an output multiplexer, control logic, and edge detection logic. The multiplexer includes inputs to receive multiple input clock signals, an output to generate the output clock signal, and a control terminal to receive a synchronized clock select signal. The control logic includes a first input to receive a clock select signal, a second input to receive a first control clock signal, a third input to receive a synchronization signal, and an output to selectively update the synchronized clock select signal with transitions in the clock select signal. The edge detection logic includes first inputs to receive the multiple input clock signals, a second input to receive a second control clock signal, and an output to generate the synchronization signal.

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U.S. Appl. No. 10/436,781, filed May 12, 2003, Kaviani et al.
U.S. Appl. No. 10/453,235, filed Jun. 2, 2003, Vadi et al.
U.S. Appl. No. 10/837,329, filed Apr. 30, 2004, Vadi et al.

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