Multiplex communications – Diagnostic testing – Fault detection
Reexamination Certificate
1999-05-18
2003-12-02
Cangialosi, Salvatore (Department: 2661)
Multiplex communications
Diagnostic testing
Fault detection
C370S244000
Reexamination Certificate
active
06657968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to a glitcher for interfaced or linked systems and in particular to an interfaced or link glitcher system and method that creates faults and simulates noisy interfaces to verify error recovery in various interfaced or linked architectures.
2. Description of the Related Art
Various types of interfaced or linked architectures exist wherein various computer systems and/or devices are coupled together in communication with each other by these various types of interfaced or linked architectures. Two main types of interfaced or linked architectures are a serial differential interfaced system and an optical interfaced system. Examples of such interfaced or linked architectures include but are not limited to serial storage architecture (SSA) (serial differential interface type), fibre channel (optical type), IEEE 1394 interface architecture, ethernet, USB, and ATM.
As an example, a serial storage architecture (SSA) system typically has a SSA initiator serially linked to and in communication with a number of target disk drives. Interfaces exist between each of the devices in the SSA system. Ensuring that the SSA system is able to properly perform error recovery in the event of a faulty link or interface between devices of the SSA system is very important.
However, simulation of a noisy interface or dirty link between interfaced or linked devices that are coupled together by an interfaced or linked architecture has been extremely difficult, especially at high speeds, in order to verify and test the error recovery performance of the interfaced or linked architecture system. A good standard conventional system or method for verifying and testing the error recovery in an interfaced or linked architecture system has not been developed and generally does not exist. Several less conventional systems and methods in verifying and testing the error recovery of such interfaces have been used or employed.
Such less conventional systems and methods have included the unplugging of links between devices or the using of faulty cables between devices to create or simulate noisy interfaces and dirty links in order to perform the error recovery testing. However, the results of unplugging a link or using a faulty or bad cable between devices is very unpredictable. Typically, the unplugging of a link or the using of a faulty or bad cable between the devices may result in either the device(s) being entirely or completely shut down or killed wherein fault simulation and error recovery testing cannot be continued or may result in no errors being generated wherein accurate fault simulation and error recovery testing cannot be achieved.
Also systems and methods for verifying whether data has been transferred between devices exist. Such systems and methods verify and check for Cyclic Redundancy Checker (CRC) errors. These systems and methods verify whether any of the bits of information within a frame has changed. Therefore, systems and methods for checking CRC errors exist, but good standard conventional systems or methods for verifying and checking data at a lower level such as verifying disparity errors (i.e. every word of data is checked whether control word, etc.) and verifying recovery from such errors generally does not exist.
It would be advantageous and desirable to provide a system and method that allows for verification of error recovery by an interfaced or linked architecture system. It would further be advantageous and desirable to provide accurate, reliable, and more assured fault simulation, such as noisy interface and dirty link simulations, within an interfaced or linked architecture system for verification of such error recovery. It would also be advantageous and desirable to have a system and method for verifying and checking data at a lower level. It would therefore be advantageous and desirable to provide a system and method for verifying recovery of disparity errors.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide a system and method that allows for verification of error recovery by an interfaced or linked architecture system.
It is another object of the present invention to provide accurate, reliable, and more assured fault simulation, such as noisy interface and dirty link simulations, within an interfaced or linked architecture system for verification of such error recovery.
It is a further object of the present invention to have a system and method for verifying and checking data at a lower level between interfaced devices.
It is still a further object of the present invention to provide a system and method for verifying disparity errors between interfaced devices.
It is another object of the present invention to be able to perform verification of error recovery between electrically linked devices or optically linked devices.
The foregoing objects are achieved as is now described. A serial differential link glitcher system and method which allow for verification of error recovery by an interfaced or linked architecture system. The system and method provide accurate, reliable, and more assured fault simulation, such as noisy interface and dirty link simulations, within an interfaced or linked architecture system for verification of such error recovery and verifies and checks data at a lower level between interfaced devices. The system and method verify disparity errors between interfaced devices and also perform verification of error recovery between electrically linked devices or optically linked devices. At least two devices are coupled together by communication lines. Normal mode allows for normal operation of and normal communication between the at least two devices, and glitch mode provides fault simulation and disparity errors and phase inversion between the at least two devices for testing error recovery of the system. Proper polarity of the communication lines is maintained between the at least two devices when the system is in normal operation mode. The polarity of the communication lines between the at least two devices is switched and inverted when the system is in glitch mode wherein phase inversion and disparity errors in the communication lines are created. The glitcher switch system comprises a switch and a control circuit. The switch allows switching between the communication mode, that is, between the normal operation mode and the glitch mode. The control circuit controls the switch in placing the system in the normal operation mode or the glitch mode.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Emberty Robert George
Klein Craig Anthony
Williams Gregory Allen
Cangialosi Salvatore
Crockatt Dale M.
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