Glitch reduction in integrated circuits, systems and methods

Details Glitch reduction in integrated circuits, systems and methods Glitch reduction in integrated circuits, systems and methods

1991-04-25

1993-02-02

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307362, 307481, H03K 1719

Patent

active

051840324

ABSTRACT:
An integrated circuit has a clock input pad and circuitry operative in response to a clock signal. Clock transitions at the clock input pad are potentially subject to glitches due to noise and ringing. Further provided is a glitch remover circuit having a logic gate having first and second inputs. The glitch remover circuit has a series of circuits coupled to the clock input pad with differing delays for positive edges than for negative edges. The series of circuits has an output connected to the first input of the logic gate, with the second input coupled to the series of circuits intermediately. Other devices, systems and methods are also disclosed.

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