Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2007-05-29
2007-05-29
Lam, David (Department: 2827)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S233100, C365S189110, C711S108000
Reexamination Certificate
active
11184346
ABSTRACT:
A glitch protect valid cell and method for maintaining a desired logic state value. The glitch protect valid cell includes a memory element, a state machine, and a glitch protect circuit. The glitch protect circuit includes a propagation delay assembly coupled to a restore assembly. The propagation delay assembly includes a first pull down network coupled to a NOR gate. The restore assembly includes a second pull down network coupled to the propagation delay assembly. Responsive to a glitch signal and timing signal, the first pull down network resets the initial state value of a true valid bit to ultimately enable a pull up network in the NOR gate. Responsive to enablement of the NOR gate pull up network, the second pull down network resets the complement valid bit in the memory element to consequently restore the initial state of the true valid bit.
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Adams Chad A.
Aipperspach Anthony G.
Behrends Derick G.
Kivimagi Ryan C.
Krentler Robert N.
International Business Machines
Lam David
Rifai D'Ann
The R. Baca Law Firm, PLLC
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