Static information storage and retrieval – Addressing – Sync/clocking
Patent
1998-08-27
2000-05-02
Nguyen, Tan T.
Static information storage and retrieval
Addressing
Sync/clocking
365194, G11C 800
Patent
active
060580704
ABSTRACT:
A glitch immune ATD circuit for electronic memory devices includes a plurality of input pads (A<0>, . . . , A<N>) of the memory device each one connected to a corresponding address input buffer (I0, . . . , IN), with each input buffer comprising an output terminal connected to a corresponding input of a local ATD generator circuit (ATD.sub.-- GEN.sub.-- LOC). The circuit also has an output for each local generator (ATD.sub.-- GEN.sub.-- LOC) connected to a corresponding input of a logic gate having a plurality (N) of inputs and an output (Y). A global ATD generator circuit has one input connected to the output (Y) of the logic gate and producing a final ATD pulse. The global ATD generator circuit includes a master slave device which is controlled by an input signal (NOTCLK) received from the output (Y) of the logic gate; a central and final ATD generator (ATD.sub.-- GEN.sub.-- END) which is connected downstream to the master-slave device; a further logic gate connected to the output of the final ATD generator and producing the final ATD pulse. The ATD circuit according to the invention is able to guarantee the minimum length Tpmin of the ATD pulse under every operating condition.
REFERENCES:
patent: 4893282 (1990-01-01), Wada et al.
patent: 5357480 (1994-10-01), Vinal
patent: 5374894 (1994-12-01), Fong
patent: 5414659 (1995-05-01), Ito
patent: 5883847 (1999-03-01), Takahashi
patent: 5894449 (1999-04-01), Jung
Galanthay Theodore E.
Nguyen Tan T.
STMicroelectronics S.r.l.
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