Glitch free power-up for a programmable array

Details Glitch free power-up for a programmable array Glitch free power-up for a programmable array

1991-08-30

1992-08-04

Mis, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307465, 307542, H03K 19003, H03K 190175

Patent

active

051361868

ABSTRACT:
Dummy circuitry, including a dummy input buffer, associated lines, and an additional row in the PLD array, provides an additional input to the PLD to keep the voltage on the bit line low until the correct input signal has fully propagated through the working input buffer and associated lines, thereby preventing a voltage glitch.

REFERENCES:
patent: 3560765 (1971-02-01), Kubinec

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