Glitch-free clock signal multiplexer circuit and method of...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – Having selection between plural continuous waveforms

Reexamination Certificate

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Details

C327S298000

Reexamination Certificate

active

07911239

ABSTRACT:
Techniques for the design and use of a digital signal processor, including for processing transmissions in a communications system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output. For a limited period of time, a low phase output level is forced. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.

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