Glitch free clock select

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

328 63, 328104, 328154, 307269, 307243, 307480, H03K 1700, H03K 513, H03K 117, H03K 1756

Patent

active

049655248

ABSTRACT:
Clock select circuitry is provided which allows CPU operation at the crystal frequency or one-half the crystal frequency. Frequency selection is accomplished under CPU control and circuitry is added to insure that the a glitch free clock change can be performed on the fly. The glitch free clock select insures that no half T state is less than what a full speed half T state would be. By gating the appropriate phases of the half speed clock and the full speed clock to control the clocking of a flip flop, the point at which the clock selection multiplexer is switched can be controlled. In speeding up the clock, the speed change occurs on the falling edge of the full speed clock provided that the half speed clock is low. When slowing down the clock, the speed change occurs on the rising edge of the half speed clock.

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Boinodiria, "Clock Synchronization For Counting Asynchronous Time Intervals", IBM Technical Disclosure Bulletin, vol. 16, No. 7, Dec. 1973, pp. 2087-2089.

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