Glitch free clock multiplexer circuit

Details Glitch free clock multiplexer circuit Glitch free clock multiplexer circuit

2000-05-03

2001-07-24

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

C327S298000

Reexamination Certificate

active

06265930

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the selection of a clock signal from a multiplicity of available clock signals.
There is a wide variety of circumstances wherein it is necessary or desirable to be able to select, by means of an appropriately coded signal, a clock signal from a multiplicity of clock signal sources. One important circumstance is in an application specific integrated circuit for use in switches or other packet-handling devices in packet-based data communication networks. However it is not intended to limit the invention by any particular context or usage.
The invention may for example be useful in network devices wherein a port may be clocked by an external clock, such as a recovered clock. It may be necessary to select between several such clocks if it is desired to multiplex between several data sources. It may also be necessary in addition to select from one or more internally generated clocks to implement loop-back or other test modes. Normally, if one did not have a guaranteed glitch-free clock multiplexer in these circumstances then the clocked circuitry would have to be reset whenever there was a change in the clock source. This generally necessitates a more complex design and may in some circumstances lead to loss of data.
BACKGROUND TO THE INVENTION
Selection schemes for clock signals exist in a wide variety of forms. A general problem in selection schemes of this nature is the achievement of switching from one clock source to another ‘on the fly’, that is to say asynchronously relative to any of the clocks without producing any ‘glitches’, that is to say undesirable transients such as spike pulses in the selected output clock signal. Various solutions to this general problem have been proposed. They generally involve negative edge clocking, asynchronous latches, asynchronously set and cleared flip-flops or gated clocks. Many designs employ some form of feedback path, for example a coupling from the output of a flip-flop to an input thereof. Although such feedback paths, exemplified by U.S. Pat. No. 4,853,653 to Maher may facilitate design from the point of view of minimising the number of gates, in general the existence of feedback paths make a design more difficult to simulate exhaustively and to analyse for edge conditions or lock-up states.
SUMMARY OF THE INVENTION
The invention is therefore primarily concerned with a selection scheme which is particularly suitable for implementation in an application specific integrated circuit having regard to the foregoing considerations.
In a preferred form of the invention, a circuit which can receive a multiplicity of clock signals is organised so that an output clock is forced ‘high’ by means of a hold signal synchronized to a currently selected clock source and is re-enabled by the removal of the hold signal, the removal of the signal being synchronous with the newly selected clock source. The effect of this arrangement is that the output clock will remain high for several clock cycles when the arrangement switches between clock sources but the ‘low’ intervals both before and after the long ‘high’ pulse will be of the correct length.
Further features of the invention will become apparent from the following detailed description with reference to the drawing.


REFERENCES:
patent: 4853653 (1989-08-01), Maher
patent: 5056120 (1991-10-01), Taniguchi et al.
patent: 5315181 (1994-05-01), Schowe
patent: 5357146 (1994-10-01), Heimann
patent: 6194939 (2001-02-01), Omas
patent: 2 287 107 (1995-09-01), None

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