Glitch-free clock multiplexer

Details Glitch-free clock multiplexer Glitch-free clock multiplexer

1992-12-31

1994-10-18

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 307510, 307518, 328104, 328137, 328154, 377 78, 377 80, H03K 513, H03K 1700

Patent

active

053571460

ABSTRACT:
A multiplexer for selecting one of at least two input signals as the output on sensing the change in the state of a select input waits for the clock signal of the active first clock to transition to a predetermined state, disconnects the active first clock from the output of the multiplexer and maintains the output of the multiplexer in the predetermined state while waiting for the clock signal of a second clock to transition to the predetermined state. The second clock is connected as the multiplexer output while the clock signal of the second clock is in the predetermined state. In a preferred embodiment, the predetermined state is a low logic level.

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patent: 5099141 (1992-03-01), Utsunomiya
patent: 5122677 (1992-06-01), Sato
patent: 5155380 (1992-10-01), Hwang et al.
patent: 5254888 (1993-10-01), Lee et al.

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