Glitch free clock enable circuit

Details Glitch free clock enable circuit Glitch free clock enable circuit

1997-04-28

1998-09-15

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By pulse width or spacing

327294, H03K 500

Patent

active

058084860

ABSTRACT:
A clock enabling circuit that generates an output clock signal such that when the enable output signal changes to a logical false, the output clock signal returns to its steady-state value in a manner that does not produce any glitches, and preserves the duty cycle of the input clock. The circuit comprises a first D flip-flop that is positive-edge triggered, a second D flip-flop that is negative-edge triggered, and a two-input AND gate. The first flip-flop has the D input connected to a constant positive voltage, the positive-edge triggered clock input connected to the input clock signal, the Q output connected to the AND gate, and the Q-complement output connected to the asynchronous reset of the second flip-flop. The second flip-flop has the D input connected to the enable output signal, the negative-edge triggered clock input connected to the input clock signal, the Q output connected to the asynchronous reset of the first flip-flop, and the Q-complement output connected to the AND gate. The output of the AND gate is the output clock signal.

REFERENCES:
patent: 5111480 (1992-05-01), Sarkoezi
patent: 5537062 (1996-07-01), Mote, Jr.

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