Glitch-free bi-phased encoder

Details Glitch-free bi-phased encoder Glitch-free bi-phased encoder

1998-07-28

2001-02-06

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from nrz codes

C327S163000, C327S166000

Reexamination Certificate

active

06184807

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of encoders, in particular to glitch-free bi-phased encoders.
BACKGROUND INFORMATION
Conventional bi-phased encoders
10
, for example, as shown in
FIG. 1
, encode input signals such as data
21
and a clock signal
22
and provide an output signal
24
, as shown in FIG.
2
. The bi-phased encoder
10
, as shown in
FIG. 1
, includes a flip-flop
11
, an inverter
12
, and an exclusive OR gate
13
. Generally, the output signal
23
provided by the flip-flop
11
includes glitches
26
. Moreover, the conventional bi-phased encoders
10
provide output signals
24
having glitches
25
. For example, conventional bi-phased encoders
10
implemented to transfer clock information and data information on one line across a high voltage interface generate glitches
25
along with the output signal
24
. The glitches
25
are created by the encoders
10
during data transitions between a high state and low state, as shown in FIG.
2
. Accordingly, the respective decoders decode the signals improperly and provide erroneous data.
Although utilizing conventional bi-phased encoders to encode signals has generally been accepted, such encoders are prone to providing output signals having glitches and are not suitable for applications requiring high accuracy and reliability.
SUMMARY OF THE INVENTION
An object of the present invention is providing a clock deglitching circuit for preventing glitches on an encoded output signal.
Another object of the present invention is providing an encoder which produces an accurate encoded signal.
It is still another object of the present invention to provide a codec interface system which accurately encodes, transmits, and decodes data.
An aspect of the present invention provides an encoder which includes a flip-flop; a first, second and third NAND gate; a first and second inverter; and a first and second delay cell. The first inverter couples the flip-flop with the first NAND gate. The first delay cell couples the first NAND gate with the third NAND gate. The second inverter couples the second delay cell with the second NAND gate. Further, the second NAND gate couples the second inverter with the third NAND gate.
Another aspect of the present invention provides a clock deglitching circuit which includes a flip-flop; a first, second and third NAND gate; a first and second inverter; and a first and second delay cell. The first inverter couples the flip-flop with the first NAND gate. The first delay cell couples the first NAND gate with the third NAND gate. The second inverter couples the second delay cell with the second NAND gate. Further, the second NAND gate couples the second inverter with the third NAND gate. The third NAND gate of the encoder produces a glitch-free encoded signal.
Still another aspect of the present invention provides a Data Access Arrangement codec interface system which includes a transmitter codec communicating with a receiver codec. The transmitter codec includes a flip-flop; a first, second and third NAND gate; a first and second inverter; and a first and second delay cell. The first inverter couples the flip-flop with the first NAND gate. The first delay cell couples the first NAND gate with the third NAND gate. The second inverter couples the second delay cell with the second NAND gate. Further, the second NAND gate couples the second inverter with the third NAND gate. The third NAND gate of the transmitter codec of the codec interface system provides a glitch-free encoded signal to the receiver codec.


REFERENCES:
patent: 4204199 (1980-05-01), Isailovic
patent: 4307381 (1981-12-01), Isailovic
patent: 4325053 (1982-04-01), Le Brozec et al.

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