Glitch eliminator circuit for TTL transparent latch

Details Glitch eliminator circuit for TTL transparent latch Glitch eliminator circuit for TTL transparent latch

1980-03-10

1981-10-27

Dixon, Harold A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307456, 307542, H03K 1756

Patent

active

042975930

ABSTRACT:
A TTL transparent latch circuit includes an input transistor having a base coupled to an input data signal and having emitter and collector terminals coupled respectively to the emitter and collector terminals of a latching transistor. A latch disabling signal is also coupled to the base of the input transistor which, when high, places the circuit in a transparent mode. An inverting gate inverts a latch enabling signal to form the latch disabling signal. The emitter of an additional transistor is coupled to the enabling signal, and the collector of the additional transistor is coupled to the base of the latching transistor. The base of the additional transistor is coupled to a source of supply voltage and to the output of the inverting gate. In this manner, the latching transistor is turned off simultaneously with turning the input transistor on.

REFERENCES:
patent: 4093878 (1978-06-01), Paschal et al.

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