Glitch detection circuit and method

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

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341132, H03M 134

Patent

active

052105385

ABSTRACT:
A glitch detection circuit having an A/D converter, a state holding circuit, a discrimination circuit and a storing circuit. The A/D converter samples an input signal at a predetermined sampling interval to produce digital data during a predetermined acquisition interval which is longer or equal to the sampling interval. The state holding circuit is connected to an output terminal of the A/D converter, and holds a distribution state of the digital data in the predetermined acquisition interval. The discrimination circuit detects a maximum value and a minimum value during the acquisition interval based on the digital data held in the state holding circuit, and the storing circuit stores the maximum value and the minimum value produced from the discrimination circuit for each acquisition interval. The arrangement can obviate the need for the feedback loop that limits the operation speed in a conventional circuit, and can detect maximum values and the minimum values by using the state holding circuit and discriminating circuit arranged in cascade. The circuit can approximately double the operation speed of a conventional circuit, and hence can double the sampling frequency of the analog-to-digital converter. A glitch of a half pulse width can be detected.

REFERENCES:
patent: 3882489 (1975-05-01), Guggolz
patent: 4211999 (1980-07-01), Clark et al.
patent: 4271486 (1981-06-01), Dagostino et al.
patent: 4611194 (1986-09-01), Konig et al.
patent: 4908622 (1990-03-01), Turai

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