Glitch detection by forcing the output of a simulated logic devi

Details Glitch detection by forcing the output of a simulated logic devi Glitch detection by forcing the output of a simulated logic devi

1986-06-26

1988-11-22

Williams, Jr., Archie E.

Boots, shoes, and leggings

371 23, G06F 1128

Patent

active

047870621

ABSTRACT:
Races and hazards in simulated logic designs are more easily detected if the logic simualtor is able to warn the designer of the presence of glitches. A glitch wall occur at the output of a logic device if an input condition causes the output to begin to change but the input condition is not present for sufficient time to allow the output to reach its stable state. The logic evaluator is the component of the logic simulator which is responsible for determining the output of a simulated device when the inputs to that device are known. The glitch detecting logic evaluator according to the present invention provides glitch detection by forcing the simulated device output to the undefined state when the device inputs change in a manner which does not allow the change to propagate to the output before a subsequent change occurs. The algorithms are designed for implementation in hardware for high performance logic simulation.

REFERENCES:
patent: 3909802 (1975-09-01), Cassarino et al.
patent: 3969722 (1976-07-01), Danco et al.
patent: 4063308 (1977-12-01), Collins et al.
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4527249 (1985-07-01), Brunt
patent: 4571724 (1986-02-01), Belmondo et al.
patent: 4587625 (1986-05-01), Marino et al.
patent: 4628471 (1986-12-01), Schuler et al.
patent: 4656580 (1987-04-01), Hitchcock
patent: 4675832 (1987-06-01), Robinson et al.
Szygenda, S., et al., "Implemental Techniques for Handling Spikes in an Assignable Delay Simulator", Proceedings of 1974 Winter Simulation Conference, Jan. 14-16, 1974, pp. 721-722.

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