Gigabit switch on chip architecture

Details Gigabit switch on chip architecture Gigabit switch on chip architecture

2006-09-05

2006-09-05

Nguyen, Brian (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S392000

Reexamination Certificate

active

07103053

ABSTRACT:
A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and an common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit. One set of communication channels provides communication from the first and second data port interfaces to the memory management unit and the other set of communication channels provides communication from the memory management unit to the first and second data port interfaces.

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