Ghost reduction circuit arrangement for a television receiver

Details Ghost reduction circuit arrangement for a television receiver Ghost reduction circuit arrangement for a television receiver

1981-12-16

1986-04-29

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

H04N 5213

Patent

active

045860831

ABSTRACT:
The output signals from the first set of delay elements of m each with a first delay time are selectively applied to a second set of delay elements of n each with a second delay time by means of a switch. The output signals from the said first and said second of delay elements are processed by the individual gain controllable circuits and are composed by an adder. The gains of the gain controllable circuits are respectively controlled by output signals from the control voltage generating circuits which are set by the output signals from comparators for comparing the television signal supplied to the input terminal with a reference signal from the reference signal generating circuit, so that the ghost interference in the television receiver can be reduced by a lesser number of delay elements by subtracting the output signals of the adder circuits from the television input signal in subtractor circuits.

REFERENCES:
patent: 4053932 (1977-10-01), Yamaguti et al.
patent: 4127874 (1978-11-01), Iwasawa et al.

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