Geometry for fabricating enhancement and depletion-type, pull-up

Details Geometry for fabricating enhancement and depletion-type, pull-up Geometry for fabricating enhancement and depletion-type, pull-up

1980-02-04

1981-11-24

Edlow, Martin H.

357 41, 357 59, 357 68, H01L 2978

Patent

active

043027652

ABSTRACT:
An improved layout for controlling the channel length of silicon gate, enhancement and depletion pull-up field effect transistor devices. The improved layout enables a transistor device to be fabricated with minimal size and at minimum channel length tolerance.

REFERENCES:
patent: 3969745 (1976-07-01), Blocker
patent: 4062039 (1977-12-01), Nishimura
patent: 4084108 (1978-04-01), Fujimoto
patent: 4125854 (1978-11-01), McKenny
patent: 4180826 (1979-12-01), Shappir
patent: 4185319 (1980-01-01), Stewart
patent: 4208670 (1980-06-01), Hoffman

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