Geometrical layout technique for a circular capacitor within an

Details Geometrical layout technique for a circular capacitor within an Geometrical layout technique for a circular capacitor within an

1998-02-13

1999-07-20

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

3612982, H07L 2941

Patent

active

059259213

ABSTRACT:
A geometrical layout technique for an individual circular capacitor in a semiconductor device. Circular capacitors reduce the detrimental effects of (1) corner etching, (2) peripheral capacitance, (3) capacitor to capacitor coupling, and (4) electric field anomalies and result in superior capacitor matching. The circular capacitor is comprised of a circular bottom plate made of a conducting material, a circular dielectric material coupled to the bottom plate and a circular top plate made of a conducting material.
The circular capacitors may be arranged as an array in either a rectangular lattice layout or a diagonal lattice layout. These lattice layouts take advantage of the elimination or reduction of the problems encountered in the prior art such as corner etching, peripheral capacitance, capacitor to capacitor coupling and electric field anomalies.

REFERENCES:
patent: 2606955 (1952-08-01), Herrick
patent: 4542444 (1985-09-01), Boland
patent: 4937096 (1990-06-01), Arakawa et al.
patent: 5241201 (1993-08-01), Matsuo et al.
patent: 5793076 (1998-08-01), Fazan et al.

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