Geometric D/A converter for a delay-locked loop

Details Geometric D/A converter for a delay-locked loop Geometric D/A converter for a delay-locked loop

2005-12-13

2005-12-13

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S120000, C341S145000

Reexamination Certificate

active

06975260

ABSTRACT:
A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)
taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.

REFERENCES:
patent: 5621685 (1997-04-01), Cernea et al.
patent: 5703588 (1997-12-01), Rivoir et al.
patent: 5949362 (1999-09-01), Tesch et al.
patent: 5977899 (1999-11-01), Adams
patent: 6154160 (2000-11-01), Meyer et al.
patent: 6476748 (2002-11-01), Galton
patent: 6489905 (2002-12-01), Lee et al.
patent: 6507296 (2003-01-01), Lee et al.

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