Geometric D/A converter for a delay-locked loop

Details Geometric D/A converter for a delay-locked loop Geometric D/A converter for a delay-locked loop

2004-03-24

2004-11-16

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S120000, C341S145000

Reexamination Certificate

active

06819278

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to digital-to-analog converters (DACs), and more particularly to a geometric D/A converter architecture that can be used to implement a delay-locked loop (DLL) with a digital control loop.
2. Description of the Prior Art
The general architecture of a DLL
100
with a digital control loop is shown in FIG.
1
. The DLL
100
includes of a delay line
102
with controllable delay (shown as a chain of buffers in the Figure). The control signal
104
is analog. DLL
100
further includes a phase detector
106
(shown as pd) which compares the input and output clock signals
108
,
110
of the delay line
102
and issues an appropriate signal in response to a mismatch. The DLL
100
also includes a filter and state machine
112
which receives the phase detector results and makes an appropriate decision with regard to any delay increase or decrease. Finally, DLL
100
can also be seen to include a D/A converter
120
(shown and referred to herein after as DAC), which converts the filter and state machine
112
results from digital format to analog, which are then fed to the delay line control line
104
.
The cells of delay line
102
can be, for example, current starved inverters, meaning that the delay of each cell is controlled by varying the amount of current available for switching. In this implementation, the output of the DAC
120
is a current. The delay of a current starved inverter is known to be proportional to C~Vdd/I, where C is the input capacitance of the gate, Vdd is the supply voltage, and I is the current supplied to the cell.
If a linear DAC
120
is employed along with the delay line
102
to provide a 1% delay resolution, for example, the 1% delay resolution should be set at the minimum current or maximum delay. Then, if for example, a delay range of 2-4 nsec is desired and if the associated process, voltage and temperature (PVT) variations and margins are assumed to be 65%, the delay resolution will be 24-40 psec at 4 nsec (0.6%-1%) and 6-10 psec at 2 nsec (0.3%-0.5%). The foregoing characteristics necessitate at least 230 taps for the DAC
120
(number of taps=(I
max
/I
min
−1)/0.01=(2×1.65−1)/0.01=230). Considering the unnecessary fine resolution at 2 nsec, this will of course result in wasted resources.
A better solution might be to implement a geometric DAC
120
, in which the current output from tap to tap increases geometrically. In the present document, the required resolution is denoted by the term (k−1). For example a resolution of 1% means that k−=0.01 or k=1.01. Then choosing:
I
0
=I
min
, i
1
=I
0
(
k−
1), i
2
=I
0
(
k−
1)
k,i
3
=I
0
(
k−
1)k
2
, . . . i
n
=I
0
(k−1)
k
−1
renders I
n
=I
0
k
n
, and
Delay ∝1/(I
0
k
n
)∝(1
/k
n
)
All of the delay steps will thus be k times apart from one another. The same 1% resolution discussed herein before can therefore now be achieved using only 120 taps.
Such a geometric DAC can be implemented simply by using a series of 120 consecutive geometrically sized transistors having 120 output switches. This type of implementation is problematic however, in that the size of the DAC
120
can become large; and in fact can be as large as the linear DAC discussed herein before. Since 120 control lines will be necessary, an appropriate shift register can be employed, but will also be problematic since it will be large and difficult to control.
The desired geometric DAC can also be implemented by summing the current from a pair of DACs. One DAC would be a sub-DAC with n output taps, each one providing the minimum current resolution. The primary DAC would have m output taps, with each tap providing the current resolution of n taps combined (k
n
−1 for a geometric DAC), where m should be (total number of taps needed)
. While this technique is easy to implement using a linear DAC, it does not render itself easily to the implementation of a geometric DAC. Considering errors in transistor sizes, this implementation can even lead to a DAC having an undesirable non-monotonic output current. Further, the overall DAC size remains undesirably the same.
It would therefore be desirable and advantageous in view of the foregoing to provide a geometric D/A architecture suitable for implementing a delay-locked loop with a digital control loop and that does not suffer the shortcomings discussed herein above.
SUMMARY OF THE INVENTION
The present invention is directed to a geometric DAC architecture. The DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)
taps. The output of each of the m taps is increased geometrically at a rate of k
n
, where k has the same meaning as the same symbol used in the background section. The geometric DAC architecture control lines desirably require only (m+n) bits compared with (m×n) bits for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations.
According to one embodiment, a digital-to-analog converter (DAC) comprises a series of substantially identical sub-DACs, each sub-DAC having n taps and (n+m) control lines; and a bias-DAC having m output taps, wherein the output of each of the m taps is increased geometrically from its immediately preceding bias-DAC output tap, and further wherein each bias-DAC output tap is configured to bias one sub-DAC.
The DAC may also comprise means for alternately inverting n control lines between sub-DACs such that any state transition associated with the DAC occurs in response to no more than a single bit change in any of the n and m control lines.
According to another embodiment, a method of controlling a geometric DAC comprises the steps of providing a geometric DAC having a plurality of substantially identical sub-DACs, a bias-DAC, and n+m control lines, wherein n=number of sub-DAC outputs and m=number of bias-DAC outputs; coding the m control lines to control which sub-DACs are active; and coding the n control lines to control which sub-DAC taps are active in association with the last known active sub-DAC.
The method of controlling a geometric DAC may also comprise of alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.


REFERENCES:
patent: 5621685 (1997-04-01), Cernea et al.
patent: 5703588 (1997-12-01), Rivoir et al.
patent: 5949362 (1999-09-01), Tesch et al.
patent: 5977899 (1999-11-01), Adams
patent: 6154160 (2000-11-01), Meyer et al.
patent: 6476748 (2002-11-01), Galton
patent: 6489905 (2002-12-01), Lee et al.
patent: 6507296 (2003-01-01), Lee et al.

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